Nefarious scheming

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+vim: set sw=8 noet :
+
+        * Checker should let us check data
+                * Fetch load
+                * Indirect load
+                * Indirect store
+                * Exec load
+                * Exec store
+        * Checker should print mismatches on its own instead
+          of depending on the caller
+                * Make it complete
+                * Make it pretty
+        * D-side cache
+                * Store forwarding
+                * Cache consistency between I and D side
+                * Senior store commit
+                * Shared between exec and indir stages
+                        * Arbitration to reduce total port count
+                * Alternative: make separate indir and exec caches, depend on
+                  cache consistency protocol
+        * Eliminate "unstores"
+        * SMC support
+                * Stores should snoop all upstream instruction PCs and restart if overlap
+        * Statistics about instruction mix
+                * Indirect loads
+                * Autoincrements
+                * Exec loads
+                * Exec stores
+                * Instructions with both exec load and exec store
+                * Instructions with both indirect and any exec memory
+                * Instructions with *three memory operations*
+                * Instructions with ~*all four memory operations*~
+                        * Maybe histogram support, instructions with N memory ops
+                * Control register writes
+                        * Per control register / bit