diff options
| author | Julian Blake Kongslie | 2022-11-02 14:04:08 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-11-02 14:04:08 -0700 |
| commit | 430ed65253573017d16fdc5f7a0aafc25b83e24d (patch) | |
| tree | 0f43f7ad6077aea0ef89652d48f1207fdd141c15 /isa/decode.cpp | |
| parent | Don't emit event traces by default (diff) | |
| download | biggolf-430ed65253573017d16fdc5f7a0aafc25b83e24d.tar.xz | |
Avoid rereading the FLAGS register; use FLAGS_SAVED for GTF.
Diffstat (limited to '')
| -rw-r--r-- | isa/decode.cpp | 37 |
1 files changed, 15 insertions, 22 deletions
diff --git a/isa/decode.cpp b/isa/decode.cpp index 77bbe8b..6ea3bb5 100644 --- a/isa/decode.cpp +++ b/isa/decode.cpp | |||
| @@ -7,9 +7,9 @@ | |||
| 7 | instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned int bits, bool interrupt) | 7 | instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned int bits, bool interrupt) |
| 8 | { | 8 | { |
| 9 | //bool gt = (flags >> 10) & 1; | 9 | //bool gt = (flags >> 10) & 1; |
| 10 | //bool ir = (flags >> 9) & 1; | 10 | bool ir = (flags >> 9) & 1; |
| 11 | //bool ii = (flags >> 8) & 1; | 11 | //bool ii = (flags >> 8) & 1; |
| 12 | //bool ie = (flags >> 7) & 1; | 12 | bool ie = (flags >> 7) & 1; |
| 13 | //bool u = (flags >> 6) & 1; | 13 | //bool u = (flags >> 6) & 1; |
| 14 | bool ifb = (flags >> 3) & 7; | 14 | bool ifb = (flags >> 3) & 7; |
| 15 | bool df = flags & 7; | 15 | bool df = flags & 7; |
| @@ -86,41 +86,37 @@ instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned i | |||
| 86 | switch (bits & 07) { | 86 | switch (bits & 07) { |
| 87 | case 0: | 87 | case 0: |
| 88 | // SKON skip if interrupts enabled | 88 | // SKON skip if interrupts enabled |
| 89 | inst.read_ctlreg = FLAGS; | ||
| 90 | inst.possibly_redirects = true; | 89 | inst.possibly_redirects = true; |
| 91 | inst.ef = [](auto &ctx) { | 90 | inst.ef = [ie](auto &ctx) { |
| 92 | if (ctx.ctlval.value() & FLAG_INT_ENABLE) | 91 | if (ie) |
| 93 | ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); | 92 | ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); |
| 94 | }; | 93 | }; |
| 95 | break; | 94 | break; |
| 96 | case 1: | 95 | case 1: |
| 97 | // ION set int_enable_delay | 96 | // ION set int_enable_delay |
| 98 | inst.read_ctlreg = FLAGS; | ||
| 99 | inst.write_ctlreg = FLAGS; | 97 | inst.write_ctlreg = FLAGS; |
| 100 | inst.ef = [](auto &ctx) { | 98 | inst.ef = [flags](auto &ctx) { |
| 101 | ctx.ctlval.value() |= FLAG_INT_ENABLE_DELAY; | 99 | ctx.ctlval = flags | FLAG_INT_ENABLE_DELAY; |
| 102 | }; | 100 | }; |
| 103 | break; | 101 | break; |
| 104 | case 2: | 102 | case 2: |
| 105 | // IOF clear int_enable and int_enable_delay | 103 | // IOF clear int_enable and int_enable_delay |
| 106 | inst.read_ctlreg = FLAGS; | ||
| 107 | inst.write_ctlreg = FLAGS; | 104 | inst.write_ctlreg = FLAGS; |
| 108 | inst.ef = [](auto &ctx) { | 105 | inst.ef = [flags](auto &ctx) { |
| 109 | ctx.ctlval.value() &= ~FLAG_INT_ENABLE_DELAY & ~FLAG_INT_ENABLE; | 106 | ctx.ctlval = flags & ~FLAG_INT_ENABLE_DELAY & ~FLAG_INT_ENABLE; |
| 110 | }; | 107 | }; |
| 111 | break; | 108 | break; |
| 112 | case 3: | 109 | case 3: |
| 113 | // SRQ skip if pending interrupt | 110 | // SRQ skip if pending interrupt |
| 114 | inst.read_ctlreg = FLAGS; | ||
| 115 | inst.possibly_redirects = true; | 111 | inst.possibly_redirects = true; |
| 116 | inst.ef = [](auto &ctx) { | 112 | inst.ef = [ir](auto &ctx) { |
| 117 | if (ctx.ctlval.value() & FLAG_INT_REQUEST) | 113 | if (ir) |
| 118 | ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); | 114 | ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); |
| 119 | }; | 115 | }; |
| 120 | break; | 116 | break; |
| 121 | case 4: | 117 | case 4: |
| 122 | // GTF get flags | 118 | // GTF get flags |
| 123 | inst.read_ctlreg = FLAGS; | 119 | inst.read_ctlreg = FLAGS_SAVED; |
| 124 | inst.need_read_link = true; | 120 | inst.need_read_link = true; |
| 125 | inst.ef = [](auto &ctx) { | 121 | inst.ef = [](auto &ctx) { |
| 126 | auto flags = ctx.ctlval.value(); | 122 | auto flags = ctx.ctlval.value(); |
| @@ -130,12 +126,11 @@ instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned i | |||
| 130 | break; | 126 | break; |
| 131 | case 5: | 127 | case 5: |
| 132 | // RTF restore flags | 128 | // RTF restore flags |
| 133 | inst.read_ctlreg = FLAGS; | ||
| 134 | inst.need_read_acc = true; | 129 | inst.need_read_acc = true; |
| 135 | inst.need_write_link = true; | 130 | inst.need_write_link = true; |
| 136 | inst.write_ctlreg = FLAGS; | 131 | inst.write_ctlreg = FLAGS; |
| 137 | inst.ef = [](auto &ctx) { | 132 | inst.ef = [ie](auto &ctx) { |
| 138 | if ((ctx.ctlval.value() & FLAG_INT_ENABLE) && (ctx.acc.value() & FLAG_INT_ENABLE)) { | 133 | if (ie && (ctx.acc.value() & FLAG_INT_ENABLE)) { |
| 139 | ctx.ctlval = ctx.acc.value() | FLAG_INT_ENABLE_DELAY; | 134 | ctx.ctlval = ctx.acc.value() | FLAG_INT_ENABLE_DELAY; |
| 140 | } else if (ctx.acc.value() & FLAG_INT_ENABLE) { | 135 | } else if (ctx.acc.value() & FLAG_INT_ENABLE) { |
| 141 | ctx.ctlval = (ctx.acc.value() | FLAG_INT_ENABLE_DELAY) & ~FLAG_INT_ENABLE; | 136 | ctx.ctlval = (ctx.acc.value() | FLAG_INT_ENABLE_DELAY) & ~FLAG_INT_ENABLE; |
| @@ -283,11 +278,9 @@ instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned i | |||
| 283 | switch (bits & 07) { | 278 | switch (bits & 07) { |
| 284 | case 01: | 279 | case 01: |
| 285 | // CDF change data field | 280 | // CDF change data field |
| 286 | inst.read_ctlreg = FLAGS; | ||
| 287 | inst.write_ctlreg = FLAGS; | 281 | inst.write_ctlreg = FLAGS; |
| 288 | inst.ef = [field](auto &ctx) { | 282 | inst.ef = [flags, field](auto &ctx) { |
| 289 | ctx.ctlval.value() &= ~FLAG_DF; | 283 | ctx.ctlval = (flags & ~FLAG_DF) | (field << FLAG_DF_SHIFT); |
| 290 | ctx.ctlval.value() |= field << FLAG_DF_SHIFT; | ||
| 291 | }; | 284 | }; |
| 292 | break; | 285 | break; |
| 293 | default: | 286 | default: |