Add initial uarch model

2 files changed, 214 insertions, 0 deletions

diff --git a/uarch/core.cpp b/uarch/core.cpp
new file mode 100644
index 0000000..34f422a
--- /dev/null
+++ b/uarch/core.cpp
@@ -0,0 +1,140 @@
+#include <fmt/format.h>
+#include <iostream>
+
+#include "uarch/core.h"
+
+fetch_stage::fetch_stage(core &c)
+    : c(c)
+    , pc(c.checker.pc)
+{ }
+
+decode_stage::decode_stage(core &c)
+    : c(c)
+    , acc(c.checker.acc)
+    , link(c.checker.link)
+    , mq(c.checker.mq)
+    , pc(c.checker.pc)
+    , ctlregs(c.checker.ctlregs)
+    , icount(c.checker.icount)
+{ }
+
+void fetch_stage::clock() {
+    if (c.fetch_restarto.has_value()) {
+        auto &r = *c.fetch_restarto;
+        pte(r.tr, "!");
+        gen = r.new_gen;
+        pc = r.new_pc;
+        didrestart = true;
+        c.fetch_restarto.reset();
+    }
+
+    if (c.fetch_bundlep.can_write()) {
+        fetch_bundle b;
+        b.tr = infra::pt::toplevel();
+        b.gen = gen;
+        b.pc = pc;
+        b.word = c.mem.fetch(pc);
+        if (didrestart)
+            infra::pt::event(b.tr, ">", now-1, "");
+        pte(b.tr, "F");
+        c.fetch_bundlep.write(std::move(b));
+        pc = (pc & 070000) | ((pc + 1) & 007777);
+        didrestart = false;
+    }
+}
+
+void decode_stage::clock() {
+    bool progress = ctlregs[HALTED];
+
+    if (!ctlregs[HALTED] && c.fetch_bundlep.can_read()) {
+        auto b = c.fetch_bundlep.read();
+
+        if (b.gen != gen)
+            goto bail_out;
+
+        if (b.pc != pc) {
+            pte(b.tr, "~");
+            fetch_restart r;
+            r.tr = b.tr;
+            r.new_gen = ++gen;
+            r.new_pc = pc;
+            c.fetch_restarto = std::move(r);
+            goto bail_out;
+        }
+
+        progress = true;
+
+        pte(b.tr, "E");
+
+        inst = decode(ctlregs[FLAGS],
+                      pc,
+                      c.mem.fetch(pc),
+                      interrupt);
+        auto next_pc = inst.next_pc;
+
+        if (inst.need_indirect_load) {
+            auto addr = c.mem.fetch(inst.init_address.value());
+            if (inst.need_autoinc_store) {
+                addr = (addr + 1) & 07777;
+                c.mem.store(*inst.init_address, addr);
+            }
+            auto df = (ctlregs[FLAGS] & FLAG_DF) >> FLAG_DF_SHIFT;
+            inst.final_address = (df << 12) | addr;
+        } else {
+            assert(!inst.need_autoinc_store);
+        }
+
+        pte(b.tr, "", inst.disasm());
+
+        if (inst.need_exec_load)
+            inst.data = c.mem.fetch(inst.final_address.value());
+
+        if (inst.need_read_acc)
+            inst.acc = acc;
+        if (inst.need_read_link)
+            inst.link = link;
+        if (inst.need_read_mq)
+            inst.mq = mq;
+        if (inst.read_ctlreg.has_value())
+            inst.ctlval = ctlregs[*inst.read_ctlreg];
+
+        inst.execute();
+
+        if (inst.need_write_acc)
+            acc = inst.acc.value();
+        if (inst.need_write_link)
+            link = inst.link.value();
+        if (inst.need_write_mq)
+            mq = inst.mq.value();
+        if (inst.write_ctlreg.has_value())
+            ctlregs[*inst.write_ctlreg] = inst.ctlval.value();
+
+        if (inst.need_exec_store)
+            c.mem.store(inst.final_address.value(), inst.data.value());
+
+        assert(inst.next_pc == next_pc || inst.possibly_redirects);
+        pc = inst.next_pc;
+    }
+bail_out:
+
+    if (progress)
+        interrupt = c.system.interact(icount++, ctlregs);
+
+    if (c.checker.icount != icount) {
+        assert(c.checker.icount + 1 == icount);
+
+        c.checker.execute();
+        assert(c.checker.icount == icount);
+        std::cerr << fmt::format("icount={:} pc={:05o} checkerpc={:05o}\n", icount, pc, c.checker.pc);
+        assert(pc == c.checker.pc);
+        assert(acc == c.checker.acc);
+        assert(link == c.checker.link);
+        assert(mq == c.checker.mq);
+        assert(ctlregs == c.checker.ctlregs);
+        if (inst.init_address.has_value())
+            assert(c.mem.fetch(*inst.init_address) == c.checker.mem.fetch(*inst.init_address));
+        if (inst.final_address.has_value())
+            assert(c.mem.fetch(*inst.final_address) == c.checker.mem.fetch(*inst.final_address));
+        assert(c.mem.fetch(pc) == c.checker.mem.fetch(pc));
+    }
+}
diff --git a/uarch/core.h b/uarch/core.h
new file mode 100644
index 0000000..0f9be74
--- /dev/null
+++ b/uarch/core.h
@@ -0,0 +1,74 @@
+#pragma once
+
+#include <array>
+
+#include "infra/pipetrace.h"
+#include "infra/port.h"
+#include "io/model.h"
+#include "isa/checker.h"
+#include "isa/isa.h"
+
+struct core;
+
+struct fetch_bundle {
+    infra::transaction tr;
+    unsigned int gen;
+    unsigned int pc;
+    unsigned int word;
+};
+
+struct fetch_restart {
+    infra::transaction tr;
+    unsigned int new_gen;
+    unsigned int new_pc;
+};
+
+struct fetch_stage : public infra::sim {
+    core &c;
+
+    unsigned int gen = 0;
+    unsigned int pc;
+    bool didrestart = false;
+
+    fetch_stage(core &c);
+
+    void clock();
+};
+
+struct decode_stage : public infra::sim {
+    core &c;
+
+    unsigned int gen = 0;
+
+    bool interrupt = false;
+
+    unsigned int acc;
+    unsigned int link;
+    unsigned int mq;
+    unsigned int pc;
+    std::array<uint_fast32_t, NUM_CTLREGS> ctlregs;
+    std::uint64_t icount;
+    instruction_context inst;
+
+    decode_stage(core &c);
+
+    void clock();
+};
+
+struct core {
+    iomodel &system;
+    funcchecker checker;
+    funcmem mem;
+
+    infra::port<fetch_bundle> fetch_bundlep;
+    std::optional<fetch_restart> fetch_restarto;
+
+    // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts)
+    decode_stage decode{*this};
+    fetch_stage fetch{*this};
+
+    core(iomodel &model)
+        : system(model)
+        , checker(model)
+    { }
+};