diff options
| -rw-r--r-- | Plan | 1 | ||||
| -rw-r--r-- | uarch/core.cpp | 3 | ||||
| -rw-r--r-- | uarch/core.h | 2 |
3 files changed, 5 insertions, 1 deletions
| @@ -1,6 +1,5 @@ | |||
| 1 | vim: set sw=8 noet : | 1 | vim: set sw=8 noet : |
| 2 | 2 | ||
| 3 | * Deadman timer | ||
| 4 | * D-side cache | 3 | * D-side cache |
| 5 | * Store forwarding | 4 | * Store forwarding |
| 6 | * Cache consistency between I and D side | 5 | * Cache consistency between I and D side |
diff --git a/uarch/core.cpp b/uarch/core.cpp index 503e286..ce58df2 100644 --- a/uarch/core.cpp +++ b/uarch/core.cpp | |||
| @@ -364,6 +364,9 @@ bail_out: | |||
| 364 | if (interrupt || oldctlregs != ctlregs) | 364 | if (interrupt || oldctlregs != ctlregs) |
| 365 | if (!restarttr.has_value()) | 365 | if (!restarttr.has_value()) |
| 366 | restarttr = infra::pt::toplevel(); | 366 | restarttr = infra::pt::toplevel(); |
| 367 | cycles_since_progress = 0; | ||
| 368 | } else { | ||
| 369 | assert(++cycles_since_progress < 10); | ||
| 367 | } | 370 | } |
| 368 | 371 | ||
| 369 | if (restarttr.has_value()) { | 372 | if (restarttr.has_value()) { |
diff --git a/uarch/core.h b/uarch/core.h index b8473e6..ebfd388 100644 --- a/uarch/core.h +++ b/uarch/core.h | |||
| @@ -78,6 +78,8 @@ struct indir_stage : public infra::sim { | |||
| 78 | struct exec_stage : public infra::sim { | 78 | struct exec_stage : public infra::sim { |
| 79 | core &c; | 79 | core &c; |
| 80 | 80 | ||
| 81 | unsigned int cycles_since_progress = 0; | ||
| 82 | |||
| 81 | unsigned int gen = 0; | 83 | unsigned int gen = 0; |
| 82 | 84 | ||
| 83 | unsigned int stores_sent = 0; | 85 | unsigned int stores_sent = 0; |
