diff options
Diffstat (limited to 'isa/decode.cpp')
| -rw-r--r-- | isa/decode.cpp | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/isa/decode.cpp b/isa/decode.cpp index 1979982..d24632b 100644 --- a/isa/decode.cpp +++ b/isa/decode.cpp | |||
| @@ -2,15 +2,21 @@ | |||
| 2 | 2 | ||
| 3 | #include "isa/isa.h" | 3 | #include "isa/isa.h" |
| 4 | 4 | ||
| 5 | instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bits) | 5 | instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bits, bool interrupt) |
| 6 | { | 6 | { |
| 7 | instruction_context inst; | ||
| 8 | |||
| 9 | auto df = dfifb >> 3; | 7 | auto df = dfifb >> 3; |
| 10 | auto ifb = dfifb & 00007; | 8 | auto ifb = dfifb & 00007; |
| 11 | 9 | ||
| 10 | instruction_context inst; | ||
| 12 | inst.next_pc = (pc & ~07777) | ((pc + 1) & 07777); | 11 | inst.next_pc = (pc & ~07777) | ((pc + 1) & 07777); |
| 13 | 12 | ||
| 13 | if (interrupt) { | ||
| 14 | bits = 04000; | ||
| 15 | assert(df == 0); | ||
| 16 | assert(ifb == 0); | ||
| 17 | inst.next_pc = pc; | ||
| 18 | } | ||
| 19 | |||
| 14 | switch (bits >> 9) { | 20 | switch (bits >> 9) { |
| 15 | case 0: // AND | 21 | case 0: // AND |
| 16 | inst.need_exec_load = true; | 22 | inst.need_exec_load = true; |
| @@ -121,6 +127,8 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit | |||
| 121 | inst.need_read_acc = sma || sza; | 127 | inst.need_read_acc = sma || sza; |
| 122 | inst.need_read_link = snl; | 128 | inst.need_read_link = snl; |
| 123 | inst.need_write_acc = cla; | 129 | inst.need_write_acc = cla; |
| 130 | if (hlt) | ||
| 131 | inst.write_ctlreg = HALTED; | ||
| 124 | inst.possibly_redirects = true; | 132 | inst.possibly_redirects = true; |
| 125 | inst.ef = [cla, sma, sza, snl, osr, hlt](auto &ctx) { | 133 | inst.ef = [cla, sma, sza, snl, osr, hlt](auto &ctx) { |
| 126 | bool skip = false; | 134 | bool skip = false; |
| @@ -129,7 +137,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit | |||
| 129 | if (snl && ctx.link.value()) skip = true; | 137 | if (snl && ctx.link.value()) skip = true; |
| 130 | if (cla) ctx.acc = 0; | 138 | if (cla) ctx.acc = 0; |
| 131 | assert(!osr); | 139 | assert(!osr); |
| 132 | if (hlt) ctx.halt = true; | 140 | if (hlt) ctx.ctlval = 1; |
| 133 | if (skip) | 141 | if (skip) |
| 134 | ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777); | 142 | ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777); |
| 135 | }; | 143 | }; |
| @@ -143,6 +151,8 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit | |||
| 143 | inst.need_read_acc = spa || sna; | 151 | inst.need_read_acc = spa || sna; |
| 144 | inst.need_read_link = szl; | 152 | inst.need_read_link = szl; |
| 145 | inst.need_write_acc = cla; | 153 | inst.need_write_acc = cla; |
| 154 | if (hlt) | ||
| 155 | inst.write_ctlreg = HALTED; | ||
| 146 | inst.possibly_redirects = true; | 156 | inst.possibly_redirects = true; |
| 147 | inst.ef = [cla, spa, sna, szl, osr, hlt](auto &ctx) { | 157 | inst.ef = [cla, spa, sna, szl, osr, hlt](auto &ctx) { |
| 148 | bool skip = true; | 158 | bool skip = true; |
| @@ -151,7 +161,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit | |||
| 151 | if (szl && ctx.link.value()) skip = false; | 161 | if (szl && ctx.link.value()) skip = false; |
| 152 | if (cla) ctx.acc = 0; | 162 | if (cla) ctx.acc = 0; |
| 153 | assert(!osr); | 163 | assert(!osr); |
| 154 | if (hlt) ctx.halt = true; | 164 | if (hlt) ctx.ctlval = 1; |
| 155 | if (skip) | 165 | if (skip) |
| 156 | ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777); | 166 | ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777); |
| 157 | }; | 167 | }; |
