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-rw-r--r--isa/decode.cpp70
1 files changed, 35 insertions, 35 deletions
diff --git a/isa/decode.cpp b/isa/decode.cpp
index 41d125d..1ecb189 100644
--- a/isa/decode.cpp
+++ b/isa/decode.cpp
@@ -18,7 +18,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
18 } 18 }
19 19
20 switch (bits >> 9) { 20 switch (bits >> 9) {
21 case 0: // AND 21 case 0: // AND bitwise and
22 inst.need_exec_load = true; 22 inst.need_exec_load = true;
23 inst.need_read_acc = true; 23 inst.need_read_acc = true;
24 inst.need_write_acc = true; 24 inst.need_write_acc = true;
@@ -26,7 +26,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
26 ctx.acc = ctx.acc.value() & ctx.data.value() & 07777; 26 ctx.acc = ctx.acc.value() & ctx.data.value() & 07777;
27 }; 27 };
28 break; 28 break;
29 case 1: // TAD 29 case 1: // TAD two's complement addition
30 inst.need_exec_load = true; 30 inst.need_exec_load = true;
31 inst.need_read_acc = true; 31 inst.need_read_acc = true;
32 inst.need_read_link = true; 32 inst.need_read_link = true;
@@ -38,7 +38,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
38 ctx.acc = sum & 07777; 38 ctx.acc = sum & 07777;
39 }; 39 };
40 break; 40 break;
41 case 2: // ISZ 41 case 2: // ISZ increment and skip if zero
42 inst.need_exec_load = true; 42 inst.need_exec_load = true;
43 inst.need_exec_store = true; 43 inst.need_exec_store = true;
44 inst.possibly_redirects = true; 44 inst.possibly_redirects = true;
@@ -48,7 +48,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
48 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); 48 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777);
49 }; 49 };
50 break; 50 break;
51 case 3: // DCA 51 case 3: // DCA deposit and clear accumulator
52 inst.need_read_acc = true; 52 inst.need_read_acc = true;
53 inst.need_write_acc = true; 53 inst.need_write_acc = true;
54 inst.need_exec_store = true; 54 inst.need_exec_store = true;
@@ -57,7 +57,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
57 ctx.acc = 0; 57 ctx.acc = 0;
58 }; 58 };
59 break; 59 break;
60 case 4: // JMS 60 case 4: // JMS jump subroutine
61 inst.need_exec_store = true; 61 inst.need_exec_store = true;
62 inst.possibly_redirects = true; 62 inst.possibly_redirects = true;
63 inst.ef = [ifb](auto &ctx) { 63 inst.ef = [ifb](auto &ctx) {
@@ -65,7 +65,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
65 ctx.next_pc = (ifb << 12) | ((ctx.final_address.value() + 1) & 07777); 65 ctx.next_pc = (ifb << 12) | ((ctx.final_address.value() + 1) & 07777);
66 }; 66 };
67 break; 67 break;
68 case 5: // JMP 68 case 5: // JMP jump
69 inst.possibly_redirects = true; 69 inst.possibly_redirects = true;
70 inst.ef = [ifb](auto &ctx) { 70 inst.ef = [ifb](auto &ctx) {
71 ctx.next_pc = (ifb << 12) | (ctx.final_address.value() & 07777); 71 ctx.next_pc = (ifb << 12) | (ctx.final_address.value() & 07777);
@@ -77,7 +77,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
77 // TELETYPE TELEPRINTER/PUNCH 77 // TELETYPE TELEPRINTER/PUNCH
78 switch (bits & 07) { 78 switch (bits & 07) {
79 case 0: 79 case 0:
80 // Set TTO flag 80 // TFL set TTO flag
81 inst.read_ctlreg = TT_BITS; 81 inst.read_ctlreg = TT_BITS;
82 inst.write_ctlreg = TT_BITS; 82 inst.write_ctlreg = TT_BITS;
83 inst.ef = [](auto &ctx) { 83 inst.ef = [](auto &ctx) {
@@ -85,7 +85,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
85 }; 85 };
86 break; 86 break;
87 case 1: 87 case 1:
88 // Skip if TTO flag is set 88 // TSF skip if TTO flag is set
89 inst.read_ctlreg = TT_BITS; 89 inst.read_ctlreg = TT_BITS;
90 inst.possibly_redirects = true; 90 inst.possibly_redirects = true;
91 inst.ef = [](auto &ctx) { 91 inst.ef = [](auto &ctx) {
@@ -94,7 +94,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
94 }; 94 };
95 break; 95 break;
96 case 2: 96 case 2:
97 // Clear TTO flag 97 // TCF clear TTO flag
98 inst.read_ctlreg = TT_BITS; 98 inst.read_ctlreg = TT_BITS;
99 inst.write_ctlreg = TT_BITS; 99 inst.write_ctlreg = TT_BITS;
100 inst.ef = [](auto &ctx) { 100 inst.ef = [](auto &ctx) {
@@ -102,7 +102,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
102 }; 102 };
103 break; 103 break;
104 case 4: 104 case 4:
105 // Print to TTO 105 // TPC print to TTO
106 inst.need_read_acc = true; 106 inst.need_read_acc = true;
107 inst.read_ctlreg = TT_BITS; 107 inst.read_ctlreg = TT_BITS;
108 inst.write_ctlreg = TT_BITS; 108 inst.write_ctlreg = TT_BITS;
@@ -115,7 +115,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
115 }; 115 };
116 break; 116 break;
117 case 5: 117 case 5:
118 // Skip if TTO flag is set or TTI flag is set 118 // TSK skip if TTO flag is set or TTI flag is set
119 inst.read_ctlreg = TT_BITS; 119 inst.read_ctlreg = TT_BITS;
120 inst.possibly_redirects = true; 120 inst.possibly_redirects = true;
121 inst.ef = [](auto &ctx) { 121 inst.ef = [](auto &ctx) {
@@ -124,7 +124,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
124 }; 124 };
125 break; 125 break;
126 case 6: 126 case 6:
127 // Print to TTO and clear TTO flag 127 // TLS print to TTO and clear TTO flag
128 inst.need_read_acc = true; 128 inst.need_read_acc = true;
129 inst.read_ctlreg = TT_BITS; 129 inst.read_ctlreg = TT_BITS;
130 inst.write_ctlreg = TT_BITS; 130 inst.write_ctlreg = TT_BITS;
@@ -150,14 +150,14 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
150 break; 150 break;
151 case 7: // OPR 151 case 7: // OPR
152 if ((bits & 0400) == 0000) { 152 if ((bits & 0400) == 0000) {
153 bool cla = bits & 0200; 153 bool cla = bits & 0200; // CLA clear accumulator
154 bool cll = bits & 0100; 154 bool cll = bits & 0100; // CLL clear link
155 bool cma = bits & 0040; 155 bool cma = bits & 0040; // CMA invert accumulator
156 bool cml = bits & 0020; 156 bool cml = bits & 0020; // CML invert link
157 bool rar = bits & 0010; 157 bool rar = bits & 0010; // RAR rotate right
158 bool ral = bits & 0004; 158 bool ral = bits & 0004; // RAL rotate left
159 bool bsw = bits & 0002; 159 bool bsw = bits & 0002; // BSW byte swap
160 bool iac = bits & 0001; 160 bool iac = bits & 0001; // IAC increment {link,accumulator}
161 inst.need_read_acc = cma || rar || ral || bsw || iac; 161 inst.need_read_acc = cma || rar || ral || bsw || iac;
162 inst.need_read_link = cml || rar || ral || iac; 162 inst.need_read_link = cml || rar || ral || iac;
163 inst.need_write_acc = cla || cma || rar || ral || bsw || iac; 163 inst.need_write_acc = cla || cma || rar || ral || bsw || iac;
@@ -190,12 +190,12 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
190 ctx.acc = ((ctx.acc.value() & 00077) << 6) | (ctx.acc.value() >> 6); 190 ctx.acc = ((ctx.acc.value() & 00077) << 6) | (ctx.acc.value() >> 6);
191 }; 191 };
192 } else if ((bits & 0411) == 0400) { 192 } else if ((bits & 0411) == 0400) {
193 bool cla = bits & 0200; 193 bool cla = bits & 0200; // CLA clear accumulator
194 bool sma = bits & 0100; 194 bool sma = bits & 0100; // SMA skip if accumulator negative
195 bool sza = bits & 0040; 195 bool sza = bits & 0040; // SZA skip if accumulator zero
196 bool snl = bits & 0020; 196 bool snl = bits & 0020; // SNL skip if link set
197 bool osr = bits & 0004; 197 bool osr = bits & 0004; // OSR bitwise or switches into accumulator
198 bool hlt = bits & 0002; 198 bool hlt = bits & 0002; // HLT halt
199 inst.need_read_acc = sma || sza; 199 inst.need_read_acc = sma || sza;
200 inst.need_read_link = snl; 200 inst.need_read_link = snl;
201 inst.need_write_acc = cla; 201 inst.need_write_acc = cla;
@@ -214,12 +214,12 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
214 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); 214 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777);
215 }; 215 };
216 } else if ((bits & 0411) == 0410) { 216 } else if ((bits & 0411) == 0410) {
217 bool cla = bits & 0200; 217 bool cla = bits & 0200; // CLA clear accumulator
218 bool spa = bits & 0100; 218 bool spa = bits & 0100; // SPA skip if accumulator positive
219 bool sna = bits & 0040; 219 bool sna = bits & 0040; // SNA skip if accumulator nonzero
220 bool szl = bits & 0020; 220 bool szl = bits & 0020; // SZL skip if link clear
221 bool osr = bits & 0004; 221 bool osr = bits & 0004; // OSR bitwise or switches into accumulator
222 bool hlt = bits & 0002; 222 bool hlt = bits & 0002; // HLT halt
223 inst.need_read_acc = spa || sna; 223 inst.need_read_acc = spa || sna;
224 inst.need_read_link = szl; 224 inst.need_read_link = szl;
225 inst.need_write_acc = cla; 225 inst.need_write_acc = cla;
@@ -238,9 +238,9 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
238 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); 238 ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777);
239 }; 239 };
240 } else if ((bits & 0401) == 0401) { 240 } else if ((bits & 0401) == 0401) {
241 bool cla = bits & 0200; 241 bool cla = bits & 0200; // CLA clear accumulator
242 bool mqa = bits & 0100; 242 bool mqa = bits & 0100; // MQA bitwise or MQ into accumulator
243 bool mql = bits & 0020; 243 bool mql = bits & 0020; // MQL copy accumulator to MQ
244 bool extended_arith = bits & 0056; 244 bool extended_arith = bits & 0056;
245 inst.need_read_acc = mqa || mql; 245 inst.need_read_acc = mqa || mql;
246 inst.need_read_mq = mqa; 246 inst.need_read_mq = mqa;
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-18 19:04:25 -0700