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-rw-r--r--uarch/core.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/uarch/core.h b/uarch/core.h
index 21725b3..b8473e6 100644
--- a/uarch/core.h
+++ b/uarch/core.h
@@ -59,7 +59,6 @@ struct decode_stage : public infra::sim {
59 std::uint64_t icount; 59 std::uint64_t icount;
60 60
61 unsigned int speculative_stores_sent = 0; 61 unsigned int speculative_stores_sent = 0;
62 unsigned int stores_done = 0;
63 62
64 decode_stage(core &c); 63 decode_stage(core &c);
65 64
@@ -114,7 +113,6 @@ struct core {
114 113
115 infra::port<memory::dram::command> decode_mem_commandp; 114 infra::port<memory::dram::command> decode_mem_commandp;
116 infra::port<memory::dram::response> decode_mem_responsep; 115 infra::port<memory::dram::response> decode_mem_responsep;
117 infra::port<memory::dram::response> decode_store_completep;
118 infra::port<inst_bundle> decode_to_exec_instp; 116 infra::port<inst_bundle> decode_to_exec_instp;
119 117
120 infra::port<inst_bundle> indir_instp; 118 infra::port<inst_bundle> indir_instp;
@@ -126,7 +124,10 @@ struct core {
126 infra::port<memory::dram::command> exec_mem_commandp; 124 infra::port<memory::dram::command> exec_mem_commandp;
127 infra::port<memory::dram::response> exec_mem_responsep; 125 infra::port<memory::dram::response> exec_mem_responsep;
128 126
129 // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts) 127 // Global counters (should be Gray code in FPGA implementation, only do == comparisons)
128 unsigned int stores_done = 0;
129
130 // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts and store count propagation)
130 exec_stage exec{*this}; 131 exec_stage exec{*this};
131 indir_stage indir{*this}; 132 indir_stage indir{*this};
132 decode_stage decode{*this}; 133 decode_stage decode{*this};