From 89c893800f908ceef46a87170ffb6ab8cb58fe0c Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sat, 22 Oct 2022 23:30:35 -0700 Subject: Improve decoder comments to directly reference instruct mnemonics --- isa/decode.cpp | 70 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/isa/decode.cpp b/isa/decode.cpp index 41d125d..1ecb189 100644 --- a/isa/decode.cpp +++ b/isa/decode.cpp @@ -18,7 +18,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit } switch (bits >> 9) { - case 0: // AND + case 0: // AND bitwise and inst.need_exec_load = true; inst.need_read_acc = true; inst.need_write_acc = true; @@ -26,7 +26,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.acc = ctx.acc.value() & ctx.data.value() & 07777; }; break; - case 1: // TAD + case 1: // TAD two's complement addition inst.need_exec_load = true; inst.need_read_acc = true; inst.need_read_link = true; @@ -38,7 +38,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.acc = sum & 07777; }; break; - case 2: // ISZ + case 2: // ISZ increment and skip if zero inst.need_exec_load = true; inst.need_exec_store = true; inst.possibly_redirects = true; @@ -48,7 +48,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); }; break; - case 3: // DCA + case 3: // DCA deposit and clear accumulator inst.need_read_acc = true; inst.need_write_acc = true; inst.need_exec_store = true; @@ -57,7 +57,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.acc = 0; }; break; - case 4: // JMS + case 4: // JMS jump subroutine inst.need_exec_store = true; inst.possibly_redirects = true; inst.ef = [ifb](auto &ctx) { @@ -65,7 +65,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.next_pc = (ifb << 12) | ((ctx.final_address.value() + 1) & 07777); }; break; - case 5: // JMP + case 5: // JMP jump inst.possibly_redirects = true; inst.ef = [ifb](auto &ctx) { ctx.next_pc = (ifb << 12) | (ctx.final_address.value() & 07777); @@ -77,7 +77,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit // TELETYPE TELEPRINTER/PUNCH switch (bits & 07) { case 0: - // Set TTO flag + // TFL set TTO flag inst.read_ctlreg = TT_BITS; inst.write_ctlreg = TT_BITS; inst.ef = [](auto &ctx) { @@ -85,7 +85,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 1: - // Skip if TTO flag is set + // TSF skip if TTO flag is set inst.read_ctlreg = TT_BITS; inst.possibly_redirects = true; inst.ef = [](auto &ctx) { @@ -94,7 +94,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 2: - // Clear TTO flag + // TCF clear TTO flag inst.read_ctlreg = TT_BITS; inst.write_ctlreg = TT_BITS; inst.ef = [](auto &ctx) { @@ -102,7 +102,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 4: - // Print to TTO + // TPC print to TTO inst.need_read_acc = true; inst.read_ctlreg = TT_BITS; inst.write_ctlreg = TT_BITS; @@ -115,7 +115,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 5: - // Skip if TTO flag is set or TTI flag is set + // TSK skip if TTO flag is set or TTI flag is set inst.read_ctlreg = TT_BITS; inst.possibly_redirects = true; inst.ef = [](auto &ctx) { @@ -124,7 +124,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 6: - // Print to TTO and clear TTO flag + // TLS print to TTO and clear TTO flag inst.need_read_acc = true; inst.read_ctlreg = TT_BITS; inst.write_ctlreg = TT_BITS; @@ -150,14 +150,14 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit break; case 7: // OPR if ((bits & 0400) == 0000) { - bool cla = bits & 0200; - bool cll = bits & 0100; - bool cma = bits & 0040; - bool cml = bits & 0020; - bool rar = bits & 0010; - bool ral = bits & 0004; - bool bsw = bits & 0002; - bool iac = bits & 0001; + bool cla = bits & 0200; // CLA clear accumulator + bool cll = bits & 0100; // CLL clear link + bool cma = bits & 0040; // CMA invert accumulator + bool cml = bits & 0020; // CML invert link + bool rar = bits & 0010; // RAR rotate right + bool ral = bits & 0004; // RAL rotate left + bool bsw = bits & 0002; // BSW byte swap + bool iac = bits & 0001; // IAC increment {link,accumulator} inst.need_read_acc = cma || rar || ral || bsw || iac; inst.need_read_link = cml || rar || ral || iac; inst.need_write_acc = cla || cma || rar || ral || bsw || iac; @@ -190,12 +190,12 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.acc = ((ctx.acc.value() & 00077) << 6) | (ctx.acc.value() >> 6); }; } else if ((bits & 0411) == 0400) { - bool cla = bits & 0200; - bool sma = bits & 0100; - bool sza = bits & 0040; - bool snl = bits & 0020; - bool osr = bits & 0004; - bool hlt = bits & 0002; + bool cla = bits & 0200; // CLA clear accumulator + bool sma = bits & 0100; // SMA skip if accumulator negative + bool sza = bits & 0040; // SZA skip if accumulator zero + bool snl = bits & 0020; // SNL skip if link set + bool osr = bits & 0004; // OSR bitwise or switches into accumulator + bool hlt = bits & 0002; // HLT halt inst.need_read_acc = sma || sza; inst.need_read_link = snl; inst.need_write_acc = cla; @@ -214,12 +214,12 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); }; } else if ((bits & 0411) == 0410) { - bool cla = bits & 0200; - bool spa = bits & 0100; - bool sna = bits & 0040; - bool szl = bits & 0020; - bool osr = bits & 0004; - bool hlt = bits & 0002; + bool cla = bits & 0200; // CLA clear accumulator + bool spa = bits & 0100; // SPA skip if accumulator positive + bool sna = bits & 0040; // SNA skip if accumulator nonzero + bool szl = bits & 0020; // SZL skip if link clear + bool osr = bits & 0004; // OSR bitwise or switches into accumulator + bool hlt = bits & 0002; // HLT halt inst.need_read_acc = spa || sna; inst.need_read_link = szl; inst.need_write_acc = cla; @@ -238,9 +238,9 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit ctx.next_pc = (ctx.next_pc & ~07777) | ((ctx.next_pc + 1) & 07777); }; } else if ((bits & 0401) == 0401) { - bool cla = bits & 0200; - bool mqa = bits & 0100; - bool mql = bits & 0020; + bool cla = bits & 0200; // CLA clear accumulator + bool mqa = bits & 0100; // MQA bitwise or MQ into accumulator + bool mql = bits & 0020; // MQL copy accumulator to MQ bool extended_arith = bits & 0056; inst.need_read_acc = mqa || mql; inst.need_read_mq = mqa; -- cgit v1.2.3