From e5240f276659a341c42e0b7da4d36bb8c150dfac Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sat, 15 Oct 2022 12:11:29 -0700
Subject: Implement most of the OPR instructions.

---
 isa/decode.cpp | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 87 insertions(+), 3 deletions(-)

diff --git a/isa/decode.cpp b/isa/decode.cpp
index 5212ae7..1d46375 100644
--- a/isa/decode.cpp
+++ b/isa/decode.cpp
@@ -66,14 +66,98 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
             };
             break;
         case 6: // IOT
-            inst.ef = [bits](auto &ctx) {
+            inst.ef = [](auto &ctx) {
                 assert(false);
             };
             break;
         case 7: // OPR
-            inst.ef = [bits](auto &ctx) {
+            if ((bits & 0400) == 0000) {
+                bool cla = bits & 0200;
+                bool cll = bits & 0100;
+                bool cma = bits & 0040;
+                bool cml = bits & 0020;
+                bool rar = bits & 0010;
+                bool ral = bits & 0004;
+                bool bsw = bits & 0002;
+                bool iac = bits & 0001;
+                inst.need_read_acc = cma || rar || ral || bsw || iac;
+                inst.need_read_link = cml || rar || ral || iac;
+                inst.need_write_acc = cla || cma || rar || ral || bsw || iac;
+                inst.need_write_link = cll || cml || rar || ral || iac;
+                inst.ef = [cla, cll, cma, cml, rar, ral, bsw, iac](auto &ctx) {
+                    if (cla) ctx.acc = 0;
+                    if (cll) ctx.link = 0;
+                    if (cma) ctx.acc = ~ctx.acc.value();
+                    if (cml) ctx.link = !ctx.link.value();
+                    if (iac) {
+                        if (++ctx.acc.value() == 0) ctx.link = !ctx.link.value();
+                    }
+                    if (rar && !ral) {
+                        unsigned int x = (ctx.link.value() << 12) | ctx.acc.value();
+                        x = (x >> 1) | ((x & 1) << 12);
+                        if (bsw)
+                            x = (x >> 1) | ((x & 1) << 12);
+                        ctx.link = x >> 12;
+                        ctx.acc = x & 07777;
+                    }
+                    if (ral && !rar) {
+                        unsigned int x = (ctx.link.value() << 12) | ctx.acc.value();
+                        x = ((x << 1) & 07777) | (x >> 12);
+                        if (bsw)
+                            x = ((x << 1) & 07777) | (x >> 12);
+                        ctx.link = x >> 12;
+                        ctx.acc = x & 07777;
+                    }
+                    if (bsw && !(rar || ral))
+                        ctx.acc = ((ctx.acc.value() & 00077) << 6) | (ctx.acc.value() >> 6);
+                };
+            } else if ((bits & 0411) == 0400) {
+                bool cla = bits & 0200;
+                bool sma = bits & 0100;
+                bool sza = bits & 0040;
+                bool snl = bits & 0020;
+                bool osr = bits & 0004;
+                bool hlt = bits & 0002;
+                inst.need_read_acc = sma || sza;
+                inst.need_read_link = snl;
+                inst.need_write_acc = cla;
+                inst.possibly_redirects = true;
+                inst.ef = [cla, sma, sza, snl, osr, hlt](auto &ctx) {
+                    bool skip = false;
+                    if (sma && (ctx.acc.value() & 04000)) skip = true;
+                    if (sza && (ctx.acc.value() == 0)) skip = true;
+                    if (snl && ctx.link.value()) skip = true;
+                    if (cla) ctx.acc = 0;
+                    assert(!osr);
+                    if (hlt) ctx.halt = true;
+                    if (skip)
+                        ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777);
+                };
+            } else if ((bits & 0411) == 0410) {
+                bool cla = bits & 0200;
+                bool spa = bits & 0100;
+                bool sna = bits & 0040;
+                bool szl = bits & 0020;
+                bool osr = bits & 0004;
+                bool hlt = bits & 0002;
+                inst.need_read_acc = spa || sna;
+                inst.need_read_link = szl;
+                inst.need_write_acc = cla;
+                inst.possibly_redirects = true;
+                inst.ef = [cla, spa, sna, szl, osr, hlt](auto &ctx) {
+                    bool skip = true;
+                    if (spa && (ctx.acc.value() & 04000)) skip = false;
+                    if (sna && (ctx.acc.value() == 0)) skip = false;
+                    if (szl && ctx.link.value()) skip = false;
+                    if (cla) ctx.acc = 0;
+                    assert(!osr);
+                    if (hlt) ctx.halt = true;
+                    if (skip)
+                        ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777);
+                };
+            } else {
                 assert(false);
-            };
+            }
             break;
     }
 
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