From 6b45e0f81267be6140f0f178579494ca6d24443b Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Mon, 31 Oct 2022 19:55:32 -0700 Subject: Restructure a lot of the control registers --- isa/decode.cpp | 45 ++++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 17 deletions(-) (limited to 'isa/decode.cpp') diff --git a/isa/decode.cpp b/isa/decode.cpp index 1496364..201a684 100644 --- a/isa/decode.cpp +++ b/isa/decode.cpp @@ -1,12 +1,18 @@ #include +#include #include #include "isa/isa.h" -instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bits, bool interrupt) +instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned int bits, bool interrupt) { - auto df = dfifb >> 3; - auto ifb = dfifb & 00007; + //bool gt = (flags >> 10) & 1; + //bool ir = (flags >> 9) & 1; + //bool ii = (flags >> 8) & 1; + //bool ie = (flags >> 7) & 1; + //bool u = (flags >> 6) & 1; + bool ifb = (flags >> 3) & 7; + bool df = flags & 7; instruction_context inst; inst.next_pc = (pc & ~07777) | ((pc + 1) & 07777); @@ -16,6 +22,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit assert(df == 0); assert(ifb == 0); inst.next_pc = pc; + pc = 0; } switch (bits >> 9) { @@ -79,42 +86,46 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit switch (bits & 07) { case 0: // SKON skip if interrupts enabled - inst.read_ctlreg = INT_ENABLE; + inst.read_ctlreg = FLAGS; inst.possibly_redirects = true; inst.ef = [](auto &ctx) { - if (ctx.ctlval.value() & 1) + if (ctx.ctlval.value() & FLAG_INT_ENABLE) ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); }; break; case 1: // ION set int_enable_delay - inst.read_ctlreg = INT_ENABLE; - inst.write_ctlreg = INT_ENABLE; + inst.read_ctlreg = FLAGS; + inst.write_ctlreg = FLAGS; inst.ef = [](auto &ctx) { - ctx.ctlval.value() |= 2; + ctx.ctlval.value() |= FLAG_INT_ENABLE_DELAY; }; break; case 2: // IOFF clear int_enable and int_enable_delay - inst.write_ctlreg = INT_ENABLE; + inst.read_ctlreg = FLAGS; + inst.write_ctlreg = FLAGS; inst.ef = [](auto &ctx) { - ctx.ctlval = 0; + ctx.ctlval.value() &= ~FLAG_INT_ENABLE_DELAY & ~FLAG_INT_ENABLE; }; break; case 3: // SRQ skip if pending interrupt - inst.read_ctlreg = INT_PENDING; + inst.read_ctlreg = FLAGS; inst.possibly_redirects = true; inst.ef = [](auto &ctx) { - if (ctx.ctlval.value()) + if (ctx.ctlval.value() & FLAG_INT_REQUEST) ctx.next_pc = (ctx.next_pc & 07777) | ((ctx.next_pc + 1) & 07777); }; break; case 4: // GTF get flags + inst.read_ctlreg = FLAGS; + inst.need_read_link = true; inst.ef = [](auto &ctx) { - std::cerr << "unimplemented GTF\n"; - assert(false); + auto flags = ctx.ctlval.value(); + flags |= (unsigned int)ctx.link.value() << 11; + ctx.acc = flags; }; break; case 5: @@ -153,11 +164,11 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit }; break; case 5: - // KIE set TT_INT_ENABLE to the low bit of the accumulator + // KIE set TT_FLAGS from the accumulator inst.need_read_acc = true; - inst.write_ctlreg = TT_INT_ENABLE; + inst.write_ctlreg = TT_FLAGS; inst.ef = [](auto &ctx) { - ctx.ctlval = ctx.acc.value() & 3; + ctx.ctlval = ctx.acc.value(); }; break; case 6: -- cgit v1.2.3