From 58da72b83d4f6ef1a729ef5fafc9cb64331af601 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 22 Jan 2023 14:27:27 -0800 Subject: Fix focal 69. (by accident, by adding a d-side cache with write-through stores, and propagating writes to the i-side cache) --- uarch/core.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'uarch/core.h') diff --git a/uarch/core.h b/uarch/core.h index ebfd388..a4ad0fe 100644 --- a/uarch/core.h +++ b/uarch/core.h @@ -38,8 +38,6 @@ struct inst_bundle { struct fetch_stage : public infra::sim { core &c; - memory::inline_cache<8, 2> cache; - unsigned int pc; bool didrestart = false; @@ -99,6 +97,10 @@ struct core { iomodel &system; funcchecker checker; + // + memory::inline_cache<8, 2> icache; + memory::inline_cache<8, 2> dcache; + std::optional restarto; unsigned int gen = 0; @@ -113,8 +115,6 @@ struct core { infra::port fetch_mem_responsep; infra::port fetch_bundlep; - infra::port decode_mem_commandp; - infra::port decode_mem_responsep; infra::port decode_to_exec_instp; infra::port indir_instp; @@ -123,7 +123,8 @@ struct core { infra::port indir_mem_responsep; infra::port indir_to_exec_instp; - infra::port exec_mem_commandp; + infra::port exec_mem_load_commandp; + infra::port exec_mem_store_commandp; infra::port exec_mem_responsep; // Global counters (should be Gray code in FPGA implementation, only do == comparisons) @@ -142,10 +143,10 @@ struct core { { mem.commandp = &mem_commandp; mem_command_arb.outp = &mem_commandp; - mem_command_arb.peerp[0] = &exec_mem_commandp; - mem_command_arb.peerp[1] = &indir_mem_store_commandp; - mem_command_arb.peerp[2] = &indir_mem_load_commandp; - mem_command_arb.peerp[3] = &decode_mem_commandp; + mem_command_arb.peerp[0] = &exec_mem_store_commandp; + mem_command_arb.peerp[1] = &exec_mem_load_commandp; + mem_command_arb.peerp[2] = &indir_mem_store_commandp; + mem_command_arb.peerp[3] = &indir_mem_load_commandp; mem_command_arb.peerp[4] = &fetch_mem_commandp; } }; -- cgit v1.2.3