From 68bdebd8cae39c30acc384664faa136aeaa9bb84 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sat, 5 Nov 2022 16:59:17 -0700
Subject: Add initial uarch model

---
 uarch/core.h | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 uarch/core.h

(limited to 'uarch/core.h')

diff --git a/uarch/core.h b/uarch/core.h
new file mode 100644
index 0000000..0f9be74
--- /dev/null
+++ b/uarch/core.h
@@ -0,0 +1,74 @@
+#pragma once
+
+#include <array>
+
+#include "infra/pipetrace.h"
+#include "infra/port.h"
+#include "io/model.h"
+#include "isa/checker.h"
+#include "isa/isa.h"
+
+struct core;
+
+struct fetch_bundle {
+    infra::transaction tr;
+    unsigned int gen;
+    unsigned int pc;
+    unsigned int word;
+};
+
+struct fetch_restart {
+    infra::transaction tr;
+    unsigned int new_gen;
+    unsigned int new_pc;
+};
+
+struct fetch_stage : public infra::sim {
+    core &c;
+
+    unsigned int gen = 0;
+    unsigned int pc;
+    bool didrestart = false;
+
+    fetch_stage(core &c);
+
+    void clock();
+};
+
+struct decode_stage : public infra::sim {
+    core &c;
+
+    unsigned int gen = 0;
+
+    bool interrupt = false;
+
+    unsigned int acc;
+    unsigned int link;
+    unsigned int mq;
+    unsigned int pc;
+    std::array<uint_fast32_t, NUM_CTLREGS> ctlregs;
+    std::uint64_t icount;
+    instruction_context inst;
+
+    decode_stage(core &c);
+
+    void clock();
+};
+
+struct core {
+    iomodel &system;
+    funcchecker checker;
+    funcmem mem;
+
+    infra::port<fetch_bundle> fetch_bundlep;
+    std::optional<fetch_restart> fetch_restarto;
+
+    // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts)
+    decode_stage decode{*this};
+    fetch_stage fetch{*this};
+
+    core(iomodel &model)
+        : system(model)
+        , checker(model)
+    { }
+};
-- 
cgit v1.2.3