From 6b7d1cdc98475f2f21002e7de5a2c563215cb279 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 15 Jan 2023 14:24:17 -0800
Subject: Reduce stalling due to stores by using a global counter.

---
 uarch/core.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'uarch/core.h')

diff --git a/uarch/core.h b/uarch/core.h
index 21725b3..b8473e6 100644
--- a/uarch/core.h
+++ b/uarch/core.h
@@ -59,7 +59,6 @@ struct decode_stage : public infra::sim {
     std::uint64_t icount;
 
     unsigned int speculative_stores_sent = 0;
-    unsigned int stores_done = 0;
 
     decode_stage(core &c);
 
@@ -114,7 +113,6 @@ struct core {
 
     infra::port<memory::dram::command> decode_mem_commandp;
     infra::port<memory::dram::response> decode_mem_responsep;
-    infra::port<memory::dram::response> decode_store_completep;
     infra::port<inst_bundle> decode_to_exec_instp;
 
     infra::port<inst_bundle> indir_instp;
@@ -126,7 +124,10 @@ struct core {
     infra::port<memory::dram::command> exec_mem_commandp;
     infra::port<memory::dram::response> exec_mem_responsep;
 
-    // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts)
+    // Global counters (should be Gray code in FPGA implementation, only do == comparisons)
+    unsigned int stores_done = 0;
+
+    // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts and store count propagation)
     exec_stage exec{*this};
     indir_stage indir{*this};
     decode_stage decode{*this};
-- 
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