uarch/core.h


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#pragma once

#include <array>

#include "infra/pipetrace.h"
#include "infra/port.h"
#include "io/model.h"
#include "isa/checker.h"
#include "isa/isa.h"

struct core;

struct fetch_bundle {
    infra::transaction tr;
    unsigned int gen;
    unsigned int pc;
    unsigned int word;
};

struct fetch_restart {
    infra::transaction tr;
    unsigned int new_gen;
    unsigned int new_pc;
};

struct fetch_stage : public infra::sim {
    core &c;

    unsigned int gen = 0;
    unsigned int pc;
    bool didrestart = false;

    fetch_stage(core &c);

    void clock();
};

struct decode_stage : public infra::sim {
    core &c;

    unsigned int gen = 0;

    bool interrupt = false;

    unsigned int acc;
    unsigned int link;
    unsigned int mq;
    unsigned int pc;
    std::array<uint_fast32_t, NUM_CTLREGS> ctlregs;
    std::uint64_t icount;
    instruction_context inst;

    decode_stage(core &c);

    void clock();
};

struct core {
    iomodel &system;
    funcchecker checker;
    funcmem mem;

    infra::port<fetch_bundle> fetch_bundlep;
    std::optional<fetch_restart> fetch_restarto;

    // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts)
    decode_stage decode{*this};
    fetch_stage fetch{*this};

    core(iomodel &model)
        : system(model)
        , checker(model)
    { }
};