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-rw-r--r--sim/tmp.sv41
1 files changed, 41 insertions, 0 deletions
diff --git a/sim/tmp.sv b/sim/tmp.sv
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index 0000000..61e35f7
--- /dev/null
+++ b/sim/tmp.sv
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1module tmp
2 #( parameter UROM = "<no file specified>"
3 , parameter UIP_BITS = 15
4 , parameter UROM_BITS = 8
5 , parameter BUS_BITS = 16
6 )
7 ( input bit clk
8 , input bit reset
9 , input bit [UIP_BITS-1:0] uip
10 , inout bit [BUS_BITS-1:0] abus
11 , inout bit [BUS_BITS-1:0] dbus
12 );
13
14bit [BUS_BITS-1:0] x;
15
16typedef enum
17 { LOAD
18 , LOAD_SEL0
19 , OUTADDR
20 , OUTDATA
21 } CtrlBit;
22
23bit [UROM_BITS-1:0] ctrl;
24urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
25
26bit [0:0] sel;
27assign sel = {ctrl[LOAD_SEL0]};
28
29assign abus = ctrl[OUTADDR] ? x : {(BUS_BITS){1'bZ}};
30assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};
31
32always @(posedge clk) begin
33 if (ctrl[LOAD]) begin
34 x <=
35 (sel == 0) ? dbus :
36 (sel == 1) ? abus :
37 {(BUS_BITS){1'bX}};
38 end
39end
40
41endmodule