From 765420c81d144bb08021a7aa09a9a0692f5d6322 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Fri, 16 Jul 2021 13:22:51 -0700 Subject: Add counter module and simplify board design for shift instructions. --- sim/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sim/alu.sv') diff --git a/sim/alu.sv b/sim/alu.sv index 407b083..5583492 100644 --- a/sim/alu.sv +++ b/sim/alu.sv @@ -49,8 +49,8 @@ assign cmp_result = {{(BUS_BITS-6){1'b0}}, abus > dbus, abus == dbus, abus < dbus}; -assign lshift_result = (dbus >= BUS_BITS) ? 0 : (abus << dbus); -assign rshift_result = (dbus >= BUS_BITS) ? 0 : (abus >> dbus); +assign lshift_result = {dbus[BUS_BITS-2:0], abus[0]}; +assign rshift_result = {abus[BUS_BITS-1], dbus[BUS_BITS-1:1]}; bit [BUS_BITS-1:0] newx; assign newx = -- cgit v1.2.3