From 765420c81d144bb08021a7aa09a9a0692f5d6322 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 16 Jul 2021 13:22:51 -0700
Subject: Add counter module and simplify board design for shift instructions.

---
 sim/control.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'sim/control.sv')

diff --git a/sim/control.sv b/sim/control.sv
index 7808f61..ddd6401 100644
--- a/sim/control.sv
+++ b/sim/control.sv
@@ -18,6 +18,7 @@ typedef enum
     { HALT
     , SET_UIP_COND
     , NOCOND
+    , ICOND
     , OUTADDR
     , OUTDATA
     } CtrlBit;
@@ -33,7 +34,7 @@ assign abus = ctrl[OUTADDR] ? constant : {(BUS_BITS){1'bZ}};
 assign dbus = ctrl[OUTDATA] ? constant : {(BUS_BITS){1'bZ}};
 
 bit cond;
-assign cond = (dbus != 0) || ctrl[NOCOND];
+assign cond = ((dbus != 0) || ctrl[NOCOND]) ^ ctrl[ICOND];
 
 always @(posedge clk) begin
     if (reset) begin
-- 
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