From 765420c81d144bb08021a7aa09a9a0692f5d6322 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 16 Jul 2021 13:22:51 -0700
Subject: Add counter module and simplify board design for shift instructions.

---
 sim/counter.sv | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 sim/counter.sv

(limited to 'sim/counter.sv')

diff --git a/sim/counter.sv b/sim/counter.sv
new file mode 100644
index 0000000..1316783
--- /dev/null
+++ b/sim/counter.sv
@@ -0,0 +1,38 @@
+module counter
+    #(  parameter   UROM        = "<no file specified>"
+    ,   parameter   UIP_BITS    = 15
+    ,   parameter   UROM_BITS   = 8
+    ,   parameter   BUS_BITS    = 16
+    )
+    (   input   bit                 clk
+    ,   input   bit                 reset
+    ,   input   bit [UIP_BITS-1:0]  uip
+    ,   inout   bit [BUS_BITS-1:0]  abus
+    ,   inout   bit [BUS_BITS-1:0]  dbus
+    );
+
+bit [BUS_BITS-1:0] x;
+
+typedef enum
+    { LOAD
+    , INCREMENT
+    , DECREMENT
+    , OUTDATA
+    } CtrlBit;
+
+bit [UROM_BITS-1:0] ctrl;
+urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
+
+assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};
+
+always @(posedge clk) begin
+    if (ctrl[LOAD]) begin
+        x <= dbus;
+    end else if (ctrl[INCREMENT]) begin
+        x <= x + 1;
+    end else if (ctrl[DECREMENT]) begin
+        x <= x - 1;
+    end
+end
+
+endmodule
-- 
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