From 60e1775b874015a3451e4bde10a8eb30701b1165 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Tue, 6 Jul 2021 09:44:36 -0700
Subject: Initial commit.

---
 sim/main.cpp | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 sim/main.cpp

(limited to 'sim/main.cpp')

diff --git a/sim/main.cpp b/sim/main.cpp
new file mode 100644
index 0000000..ac4befa
--- /dev/null
+++ b/sim/main.cpp
@@ -0,0 +1,61 @@
+#include <cstdint>
+#include <iostream>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include "Vtop.h"
+
+std::uint64_t phases = 0;
+
+double sc_time_stamp()
+{
+    return (double)phases / 2;
+}
+
+int main(int argc, const char *argv[])
+{
+    Verilated::commandArgs(argc, argv);
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC vcd;
+
+    Vtop top;
+    top.trace(&vcd, 100 /* levels of hierarchy */);
+
+    vcd.set_time_unit("ns");
+    vcd.set_time_resolution("ns");
+    vcd.open("build/out.vcd");
+
+    std::cout << "*** RESET SEQUENCE ***\n";
+
+    top.clk = 0;
+    top.reset = 1;
+    top.eval();
+    vcd.dump(++phases);
+
+    top.clk = 1;
+    top.eval();
+    vcd.dump(++phases);
+
+    top.clk = 0;
+    top.reset = 0;
+    top.eval();
+    vcd.dump(++phases);
+
+    std::cout << "*** MAIN LOOP ***\n";
+
+    for (unsigned int i = 0; i < 10000 && !Verilated::gotFinish(); ++i) {
+        top.clk = 1;
+        top.eval();
+        vcd.dump(++phases);
+        top.clk = 0;
+        top.eval();
+        vcd.dump(++phases);
+    }
+
+    std::cout << "\n";
+
+    vcd.close();
+
+    return 0;
+}
-- 
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