From 60e1775b874015a3451e4bde10a8eb30701b1165 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Tue, 6 Jul 2021 09:44:36 -0700
Subject: Initial commit.

---
 sim/pc.sv | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 sim/pc.sv

(limited to 'sim/pc.sv')

diff --git a/sim/pc.sv b/sim/pc.sv
new file mode 100644
index 0000000..1a3aaee
--- /dev/null
+++ b/sim/pc.sv
@@ -0,0 +1,36 @@
+module pc
+    #(  parameter   UROM        = "<no file specified>"
+    ,   parameter   UIP_BITS    = 15
+    ,   parameter   UROM_BITS   = 8
+    ,   parameter   BUS_BITS    = 16
+    ,   parameter   RESET       = 0
+    )
+    (   input   bit                 clk
+    ,   input   bit                 reset
+    ,   input   bit [UIP_BITS-1:0]  uip
+    ,   inout   bit [BUS_BITS-1:0]  abus
+    ,   inout   bit [BUS_BITS-1:0]  dbus
+    );
+
+bit [BUS_BITS-1:0] addr;
+
+typedef enum
+    { LOAD
+    , INCREMENT
+    , OUTADDR
+    } CtrlBit;
+
+bit [UROM_BITS-1:0] ctrl;
+urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
+
+assign abus = ctrl[OUTADDR] ? addr : {(BUS_BITS){1'bZ}};
+
+always @(posedge clk) begin
+    if (reset) begin
+        addr <= RESET;
+    end else begin
+        addr <= (ctrl[LOAD] ? abus : addr) + (ctrl[INCREMENT] ? 1 : 0);
+    end
+end
+
+endmodule
-- 
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