From 60e1775b874015a3451e4bde10a8eb30701b1165 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Tue, 6 Jul 2021 09:44:36 -0700
Subject: Initial commit.

---
 sim/rf.sv | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 sim/rf.sv

(limited to 'sim/rf.sv')

diff --git a/sim/rf.sv b/sim/rf.sv
new file mode 100644
index 0000000..37502ce
--- /dev/null
+++ b/sim/rf.sv
@@ -0,0 +1,39 @@
+module rf
+    #(  parameter   UROM        = "<no file specified>"
+    ,   parameter   UIP_BITS    = 15
+    ,   parameter   UROM_BITS   = 8
+    ,   parameter   BUS_BITS    = 16
+    ,   parameter   NAME_BITS   = 3
+    )
+    (   input   bit                 clk
+    ,   input   bit                 reset
+    ,   input   bit [UIP_BITS-1:0]  uip
+    ,   inout   bit [BUS_BITS-1:0]  abus
+    ,   inout   bit [BUS_BITS-1:0]  dbus
+    );
+
+bit [BUS_BITS-1:0] storage [0:(1<<NAME_BITS)-1];
+
+typedef enum
+    { STORE
+    , RESET
+    , OUTDATA
+    } CtrlBit;
+
+bit [UROM_BITS-1:0] ctrl;
+urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
+
+assign dbus = ctrl[OUTDATA] ? storage[abus[NAME_BITS-1:0]] : {(BUS_BITS){1'bZ}};
+
+always @(posedge clk) begin
+    if (reset || ctrl[RESET]) begin
+        for (int i = 0; i < (1 << NAME_BITS); ++i)
+            storage[i] <= 0;
+    end else begin
+        if (ctrl[STORE]) begin
+            storage[abus[NAME_BITS-1:0]] <= dbus;
+        end
+    end
+end
+
+endmodule
-- 
cgit v1.2.3