module control
    #(  parameter   UROM        = "<no file specified>"
    ,   parameter   UIP_BITS    = 15
    ,   parameter   UROM_BITS   = 8
    ,   parameter   BUS_BITS    = 16
    ,   parameter   CONST_0     = "<no file specified>"
    ,   parameter   CONST_1     = "<no file specified>"
    ,   parameter   RESET       = ~0
    )
    (   input   bit                 clk
    ,   input   bit                 reset
    ,   output  bit [UIP_BITS-1:0]  uip
    ,   inout   bit [BUS_BITS-1:0]  abus
    ,   inout   bit [BUS_BITS-1:0]  dbus
    );

typedef enum
    { HALT
    , SET_UIP_COND
    , NOCOND
    , ICOND
    , OUTADDR
    , OUTDATA
    } CtrlBit;

bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);

bit [UROM_BITS*2-1:0] constant;
urom#(CONST_0, UIP_BITS, UROM_BITS) const_0(uip, constant[1*UROM_BITS-1:0*UROM_BITS]);
urom#(CONST_1, UIP_BITS, UROM_BITS) const_1(uip, constant[2*UROM_BITS-1:1*UROM_BITS]);

assign abus = ctrl[OUTADDR] ? constant : {(BUS_BITS){1'bZ}};
assign dbus = ctrl[OUTDATA] ? constant : {(BUS_BITS){1'bZ}};

bit cond;
assign cond = ((dbus != 0) || ctrl[NOCOND]) ^ ctrl[ICOND];

always @(posedge clk) begin
    if (reset) begin
        uip <= RESET;
    end else begin
        if (! ctrl[HALT]) begin
            if (ctrl[SET_UIP_COND] && cond) begin
                uip <= abus[UIP_BITS-1:0];
            end else begin
                uip <= uip + 1;
            end
        end else begin
            $finish;
        end
    end
end

endmodule