module memory
    #(  parameter   UROM        = "<no file specified>"
    ,   parameter   UIP_BITS    = 15
    ,   parameter   UROM_BITS   = 8
    ,   parameter   BUS_BITS    = 16
    ,   parameter   IMAGE       = "<no file specified>"
    ,   parameter   BYTE_BITS   = 8
    )
    (   input   bit                 clk
    ,   input   bit                 reset
    ,   input   bit [UIP_BITS-1:0]  uip
    ,   inout   bit [BUS_BITS-1:0]  abus
    ,   inout   bit [BUS_BITS-1:0]  dbus
    );

bit [BYTE_BITS-1:0] storage [0:(1<<BUS_BITS)-1];
initial $readmemh(IMAGE, storage);

typedef enum
    { STORE
    , OUTDATA
    } CtrlBit;

bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);

assign dbus = ctrl[OUTDATA] ? {{(BUS_BITS-BYTE_BITS){1'b0}}, storage[abus]} : {(BUS_BITS){1'bZ}};

always @(posedge clk) begin
    if (ctrl[STORE]) begin
        storage[abus] <= dbus[BYTE_BITS-1:0];
    end
end

endmodule