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authorJulian Blake Kongslie2022-07-02 13:45:09 -0700
committerJulian Blake Kongslie2022-07-02 13:45:09 -0700
commitc72951a36d6cb9775dc1ecd9bc26bc13e796f10c (patch)
tree5a8fe196beba5c7c674d1b3d627c9a0beac849f5 /uarch/fetch.h
parentTrivial code reorg. (diff)
downloadissim-c72951a36d6cb9775dc1ecd9bc26bc13e796f10c.tar.xz
Dropping the async interface, and adding some real uarch.
Diffstat (limited to '')
-rw-r--r--uarch/fetch.h28
1 files changed, 28 insertions, 0 deletions
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1#pragma once
2
3#include <memory>
4
5#include "aisa/aisa.h"
6#include "aisa/simple-models.h"
7#include "sim/sim.h"
8#include "sim/queue.h"
9#include "uarch/types.h"
10
11namespace uarch {
12
13 struct FetchStage : public sim::Schedulable, aisa::TaskStack, aisa::VectorRF {
14 sim::Queue<FillReq> &fillreqq;
15 sim::Queue<Fill> &fillq;
16 sim::Queue<Uop> &uopq;
17
18 std::unique_ptr<const aisa::Step> step;
19 aisa::Wires wires;
20 bool outstanding_fill = false;
21 bool fill_complete = false;
22
23 FetchStage(sim::Scheduler &scheduler, const aisa::ISA &isa, sim::Queue<FillReq> &fillreqq, sim::Queue<Fill> &fillq, sim::Queue<Uop> &uopq);
24
25 void clock() override;
26 };
27
28}