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-rw-r--r--muckle.kicad_pro326
1 files changed, 326 insertions, 0 deletions
diff --git a/muckle.kicad_pro b/muckle.kicad_pro
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@@ -0,0 +1,326 @@
1{
2 "board": {
3 "design_settings": {
4 "defaults": {
5 "board_outline_line_width": 0.1,
6 "copper_line_width": 0.2,
7 "copper_text_size_h": 1.5,
8 "copper_text_size_v": 1.5,
9 "copper_text_thickness": 0.3,
10 "other_line_width": 0.15,
11 "silk_line_width": 0.15,
12 "silk_text_size_h": 1.0,
13 "silk_text_size_v": 1.0,
14 "silk_text_thickness": 0.15
15 },
16 "diff_pair_dimensions": [],
17 "drc_exclusions": [],
18 "rules": {
19 "min_copper_edge_clearance": 0.0,
20 "solder_mask_clearance": 0.0,
21 "solder_mask_min_width": 0.0
22 },
23 "track_widths": [],
24 "via_dimensions": []
25 },
26 "layer_presets": []
27 },
28 "boards": [],
29 "cvpcb": {
30 "equivalence_files": []
31 },
32 "erc": {
33 "erc_exclusions": [],
34 "meta": {
35 "version": 0
36 },
37 "pin_map": [
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206 ],
207 "rule_severities": {
208 "bus_definition_conflict": "error",
209 "bus_entry_needed": "error",
210 "bus_label_syntax": "error",
211 "bus_to_bus_conflict": "error",
212 "bus_to_net_conflict": "error",
213 "different_unit_footprint": "error",
214 "different_unit_net": "error",
215 "duplicate_reference": "error",
216 "duplicate_sheet_names": "error",
217 "extra_units": "error",
218 "global_label_dangling": "warning",
219 "hier_label_mismatch": "error",
220 "label_dangling": "error",
221 "lib_symbol_issues": "warning",
222 "multiple_net_names": "warning",
223 "net_not_bus_member": "warning",
224 "no_connect_connected": "warning",
225 "no_connect_dangling": "warning",
226 "pin_not_connected": "error",
227 "pin_not_driven": "error",
228 "pin_to_pin": "warning",
229 "power_pin_not_driven": "error",
230 "similar_labels": "warning",
231 "unannotated": "error",
232 "unit_value_mismatch": "error",
233 "unresolved_variable": "error",
234 "wire_dangling": "error"
235 }
236 },
237 "libraries": {
238 "pinned_footprint_libs": [],
239 "pinned_symbol_libs": []
240 },
241 "meta": {
242 "filename": "muckle.kicad_pro",
243 "version": 1
244 },
245 "net_settings": {
246 "classes": [
247 {
248 "bus_width": 12.0,
249 "clearance": 0.2,
250 "diff_pair_gap": 0.25,
251 "diff_pair_via_gap": 0.25,
252 "diff_pair_width": 0.2,
253 "line_style": 0,
254 "microvia_diameter": 0.3,
255 "microvia_drill": 0.1,
256 "name": "Default",
257 "pcb_color": "rgba(0, 0, 0, 0.000)",
258 "schematic_color": "rgba(0, 0, 0, 0.000)",
259 "track_width": 0.25,
260 "via_diameter": 0.8,
261 "via_drill": 0.4,
262 "wire_width": 6.0
263 }
264 ],
265 "meta": {
266 "version": 2
267 },
268 "net_colors": null
269 },
270 "pcbnew": {
271 "last_paths": {
272 "gencad": "",
273 "idf": "",
274 "netlist": "",
275 "specctra_dsn": "",
276 "step": "",
277 "vrml": ""
278 },
279 "page_layout_descr_file": ""
280 },
281 "schematic": {
282 "annotate_start_num": 0,
283 "drawing": {
284 "default_line_thickness": 6.0,
285 "default_text_size": 50.0,
286 "field_names": [],
287 "intersheets_ref_own_page": false,
288 "intersheets_ref_prefix": "",
289 "intersheets_ref_short": false,
290 "intersheets_ref_show": false,
291 "intersheets_ref_suffix": "",
292 "junction_size_choice": 3,
293 "label_size_ratio": 0.375,
294 "pin_symbol_size": 25.0,
295 "text_offset_ratio": 0.15
296 },
297 "legacy_lib_dir": "",
298 "legacy_lib_list": [],
299 "meta": {
300 "version": 1
301 },
302 "net_format_name": "",
303 "ngspice": {
304 "fix_include_paths": true,
305 "fix_passive_vals": false,
306 "meta": {
307 "version": 0
308 },
309 "model_mode": 0,
310 "workbook_filename": ""
311 },
312 "page_layout_descr_file": "blank.kicad_wks",
313 "plot_directory": "",
314 "spice_adjust_passive_values": false,
315 "spice_external_command": "spice \"%I\"",
316 "subpart_first_id": 65,
317 "subpart_id_separator": 0
318 },
319 "sheets": [
320 [
321 "e63e39d7-6ac0-4ffd-8aa3-1841a4541b55",
322 ""
323 ]
324 ],
325 "text_variables": {}
326}
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-18 23:02:14 -0700