From a516d4656c3acc8ca71c225c52e5e58b7e88f23c Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sat, 2 Apr 2022 09:47:27 -0700
Subject: Complete DDR4 connector footprint.

---
 muckle.kicad_pro                                   | 106 +++++-
 ...DDR4 Connector (288 pin 0.85mm pitch).kicad_mod | 414 ++++++++++++++++-----
 2 files changed, 420 insertions(+), 100 deletions(-)

diff --git a/muckle.kicad_pro b/muckle.kicad_pro
index 2700ea4..1e907c1 100644
--- a/muckle.kicad_pro
+++ b/muckle.kicad_pro
@@ -2,26 +2,120 @@
   "board": {
     "design_settings": {
       "defaults": {
-        "board_outline_line_width": 0.1,
-        "copper_line_width": 0.2,
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
         "copper_text_size_h": 1.5,
         "copper_text_size_v": 1.5,
         "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
         "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
         "silk_line_width": 0.15,
+        "silk_text_italic": false,
         "silk_text_size_h": 1.0,
         "silk_text_size_v": 1.0,
-        "silk_text_thickness": 0.15
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
       },
       "diff_pair_dimensions": [],
       "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
       "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
         "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
         "solder_mask_clearance": 0.0,
-        "solder_mask_min_width": 0.0
+        "solder_mask_min_width": 0.0,
+        "use_height_for_length_calcs": true
       },
       "track_widths": [],
-      "via_dimensions": []
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
     },
     "layer_presets": []
   },
@@ -276,7 +370,7 @@
       "step": "",
       "vrml": ""
     },
-    "page_layout_descr_file": ""
+    "page_layout_descr_file": "blank.kicad_wks"
   },
   "schematic": {
     "annotate_start_num": 0,
diff --git a/muckle.pretty/DDR4 Connector (288 pin 0.85mm pitch).kicad_mod b/muckle.pretty/DDR4 Connector (288 pin 0.85mm pitch).kicad_mod
index f3cd618..074aecb 100644
--- a/muckle.pretty/DDR4 Connector (288 pin 0.85mm pitch).kicad_mod	
+++ b/muckle.pretty/DDR4 Connector (288 pin 0.85mm pitch).kicad_mod	
@@ -1,94 +1,320 @@
-(footprint "DDR4 Connector (288 pin 0.85mm pitch)" (version 20211014) (generator pcbnew)
-  (layer "F.Cu")
-  (tedit 0)
-  (attr through_hole)
-  (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS")
-    (effects (font (size 1 1) (thickness 0.15)))
-    (tstamp d0d2eee9-31f6-44fa-8149-ebb4dc2dc0dc)
-  )
-  (fp_text value "DDR4 Connector (288 pin 0.85mm pitch)" (at 0 1 unlocked) (layer "F.Fab")
-    (effects (font (size 1 1) (thickness 0.15)))
-    (tstamp ee41cb8e-512d-41d2-81e1-3c50fff32aeb)
-  )
-  (fp_text user "${REFERENCE}" (at 0 2.5 unlocked) (layer "F.Fab")
-    (effects (font (size 1 1) (thickness 0.15)))
-    (tstamp 1e518c2a-4cb7-4599-a1fa-5b9f847da7d3)
-  )
-  (pad "1" thru_hole circle (at 0.85 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 101ef598-601d-400e-9ef6-d655fbb1dbfa))
-  (pad "2" thru_hole circle (at 1.7 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 57276367-9ce4-4738-88d7-6e8cb94c966c))
-  (pad "3" thru_hole circle (at 2.55 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp c3b3d7f4-943f-4cff-b180-87ef3e1bcbff))
-  (pad "4" thru_hole circle (at 3.4 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 96de0051-7945-413a-9219-1ab367546962))
-  (pad "5" thru_hole circle (at 4.25 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 802c2dc3-ca9f-491e-9d66-7893e89ac34c))
-  (pad "6" thru_hole circle (at 5.1 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 7d76d925-f900-42af-a03f-bb32d2381b09))
-  (pad "7" thru_hole circle (at 5.95 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 593b8647-0095-46cc-ba23-3cf2a86edb5e))
-  (pad "8" thru_hole circle (at 6.8 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 4e27930e-1827-4788-aa6b-487321d46602))
-  (pad "9" thru_hole circle (at 7.65 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 2e90e294-82e1-45da-9bf1-b91dfe0dc8f6))
-  (pad "10" thru_hole circle (at 8.5 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp ae0e6b31-27d7-4383-a4fc-7557b0a19382))
-  (pad "11" thru_hole circle (at 9.35 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp cebb9021-66d3-4116-98d4-5e6f3c1552be))
-  (pad "12" thru_hole circle (at 10.2 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 9b6bb172-1ac4-440a-ac75-c1917d9d59c7))
-  (pad "13" thru_hole circle (at 11.05 -2.7) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp d7e4abd8-69f5-4706-b12e-898194e5bf56))
-  (pad "14" thru_hole circle (at 11.9 -5.4) (size 0.75 0.75) (drill 0.5) (layers *.Cu *.Mask) (tstamp 04cf2f2c-74bf-400d-b4f6-201720df00ed))
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-)
+(footprint "DDR4 Connector (288 pin 0.85mm pitch)" (version 20211014) (generator pcbnew)
+  (layer "F.Cu")
+  (tedit 0)
+  (attr through_hole)
+  (fp_text reference "REF**" (at 0 5.25 unlocked) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp d0d2eee9-31f6-44fa-8149-ebb4dc2dc0dc)
+  )
+  (fp_text value "DDR4 Connector (288 pin 0.85mm pitch)" (at 0 -5.25 unlocked) (layer "F.Fab")
+    (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp ee41cb8e-512d-41d2-81e1-3c50fff32aeb)
+  )
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cgit v1.2.3