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<title>multipdp8/Makefile, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<updated>2022-06-05T22:42:26Z</updated>
<entry>
<title>Working L1 cache.</title>
<updated>2022-06-05T22:42:26Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-06-05T22:34:23Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>Support for downloading PAL programs.</title>
<updated>2022-06-05T20:22:00Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-06-05T20:21:25Z</published>
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<id>urn:sha1:d1830be773a24a9808e713db5229fbc93d82fa36</id>
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</content>
</entry>
<entry>
<title>Add makefile target for uploading "raw UART" images</title>
<updated>2022-05-29T23:32:08Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-05-29T23:32:08Z</published>
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<id>urn:sha1:67103bc7dac1aa510ce9a2c63d9cd58cb527606a</id>
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</content>
</entry>
<entry>
<title>Change makefile to unconditionally load memory for 16 PDP-8s</title>
<updated>2022-05-15T22:47:57Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-05-15T22:47:57Z</published>
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</content>
</entry>
<entry>
<title>*Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.</title>
<updated>2022-05-08T22:51:35Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-05-08T22:51:35Z</published>
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<id>urn:sha1:38c5ae5b60eae9562b97da42f47af3861847f8e5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Attempt to download for 16 PDP-8s.</title>
<updated>2022-03-27T23:57:46Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-03-27T23:57:46Z</published>
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<id>urn:sha1:5d3de69acf2f3ebcf5448daaa664627b70768c20</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~</title>
<updated>2022-03-21T00:27:41Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-03-21T00:27:41Z</published>
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<id>urn:sha1:3a65ecf1581148b0c09e85c58019d017e78f1857</id>
<content type='text'>
It looks like we could probably fit 16 on the current FPGA, just about.

(doesn't meet timing at 50MHz, should in theory work at 40MHz)
</content>
</entry>
<entry>
<title>Initial commit.</title>
<updated>2022-02-28T01:21:05Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-02-28T01:21:05Z</published>
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