multipdp8/hdl/defs.svh, branch main Unnamed repository; edit this file 'description' to name the repository. https://git.jblake.org/multipdp8/atom?h=main 2022-07-24T21:59:03Z Writeback cache using explicit altsyncram instead of inferred memory. 2022-07-24T21:59:03Z Julian Blake Kongslie 2022-07-24T21:59:03Z urn:sha1:1aeb760d093189486efbf5adf3292881eda94eb0 Rename memory message types for more clarity. 2022-07-10T21:23:22Z Julian Blake Kongslie 2022-07-10T21:23:22Z urn:sha1:641151b7123c4e5dbbb95392f65c0f3960fc0fef Working L1 cache. 2022-06-05T22:42:26Z Julian Blake Kongslie 2022-06-05T22:34:23Z urn:sha1:9ce65b7d3573d92e1d98a13b58a5d5763ba073c5 Two-cycle memory arbiter, enabling 16 PDP-8s @ 50MHz. 2022-05-23T00:09:03Z Julian Blake Kongslie 2022-05-23T00:09:03Z urn:sha1:085e5ceac41833f197c6cebda1c0ec925c59fb8b Working (but very slow) RS232 UART 2022-04-17T22:58:55Z Julian Blake Kongslie 2022-04-17T22:57:29Z urn:sha1:1bc6bb6857357e3cd2b3756bd9608db86e1fa456 12 PDP-8s! :-) 2022-03-28T00:00:57Z Julian Blake Kongslie 2022-03-28T00:00:57Z urn:sha1:c0d7b3cce5c0800ea4fc808f7b633562e61078eb Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~ 2022-03-21T00:27:41Z Julian Blake Kongslie 2022-03-21T00:27:41Z urn:sha1:3a65ecf1581148b0c09e85c58019d017e78f1857 It looks like we could probably fit 16 on the current FPGA, just about. (doesn't meet timing at 50MHz, should in theory work at 40MHz) Adding packed keyword to structs and tweaking tag_t slightly. 2022-03-13T23:48:23Z Julian Blake Kongslie 2022-03-13T23:48:23Z urn:sha1:d52d27e768e40de60c20b03405dc0431077bf76b Initial commit. 2022-02-28T01:21:05Z Julian Blake Kongslie 2022-02-28T01:21:05Z urn:sha1:0553c4839c06011bd044f69b4913e5c793fdd2ec