multipdp8/hdl/fifo.sv, branch main Unnamed repository; edit this file 'description' to name the repository. https://git.jblake.org/multipdp8/atom?h=main 2022-06-05T22:42:26Z Working L1 cache. 2022-06-05T22:42:26Z Julian Blake Kongslie 2022-06-05T22:34:23Z urn:sha1:9ce65b7d3573d92e1d98a13b58a5d5763ba073c5 Refer to wrap bits instead of previous greycode in FIFO greycode calculation. 2022-04-17T23:13:26Z Julian Blake Kongslie 2022-04-17T23:13:26Z urn:sha1:3ea86730def6bd637598c0cd0de9c772246b29d3 Integrate wrap bits into grey code for FIFO. 2022-03-28T17:36:35Z Julian Blake Kongslie 2022-03-28T17:36:35Z urn:sha1:6aff3f26db8d8477ed7cab43b9dc03473627b172 Don't use SystemVerilog parametric types because Altera doesn't support them. 2022-03-27T19:06:55Z Julian Blake Kongslie 2022-03-27T19:06:55Z urn:sha1:c2ead363d48ec32d6e3a1d1271a4de895a8753e5 Add basic clock-domain-crossing FIFO. 2022-03-26T16:50:26Z Julian Blake Kongslie 2022-03-26T16:50:26Z urn:sha1:4541224c007a1818ffdcd69a7dc4a8e5392bb44d