multipdp8/hdl/rs232.sv, branch main Unnamed repository; edit this file 'description' to name the repository. https://git.jblake.org/multipdp8/atom?h=main 2022-05-22T22:42:55Z Only sample RS232 signals once per clock; use a delayed flop internally. 2022-05-22T22:42:55Z Julian Blake Kongslie 2022-05-22T22:42:55Z urn:sha1:d6d6edfd57c3dc4db01666034d11ac84d31ec2ef This removes metastability issues on inputs and makes everything work. Fix the RS232 receive state machine 😠💢:mad: 2022-05-15T22:53:36Z Julian Blake Kongslie 2022-05-15T22:53:36Z urn:sha1:716ed41a46aea2a3c81564b6e6a55e3b3e43ec46 Our current consensus is that we have a bug which causes the RX state machine to make incomprehensible jumps when the sample counter is more than about 9 bits wide. We haven't completely pinned down the problem; we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter. I hate Verilog and Altera, both exclusively and in combination. Only phase shift the RS232 tx clock when we are between bytes. 2022-05-15T22:52:01Z Julian Blake Kongslie 2022-05-15T22:52:01Z urn:sha1:c3dd0394c82716f1aeccda7042fbe9baec42aa22 Consistent RS232 wire names (DCE side names is used everywhere) 2022-05-15T22:50:21Z Julian Blake Kongslie 2022-05-15T22:50:21Z urn:sha1:c9697a5bc6e315be8441223fbb07d00e57547e2f Demand that CTS is asserted for multiple symbol periods before transmit. 2022-05-09T00:20:57Z Julian Blake Kongslie 2022-05-09T00:20:57Z urn:sha1:1a47b552cca074b47c048c3428c92dfb2e3f23b1 *Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS. 2022-05-08T22:51:35Z Julian Blake Kongslie 2022-05-08T22:51:35Z urn:sha1:38c5ae5b60eae9562b97da42f47af3861847f8e5 Oversample RS232 RX uart. 2022-04-23T05:54:57Z Julian Blake Kongslie 2022-04-23T05:54:57Z urn:sha1:8dd900cb724d7d47560414d17f1be440817a0bd1 Asynchronous reset on RS232 uart. 2022-04-23T05:54:26Z Julian Blake Kongslie 2022-04-23T05:54:26Z urn:sha1:218fccd59b9750c87907917de245d3b72a518768 Transmit and receive an even parity bit in RS232 uart. 2022-04-23T05:43:36Z Julian Blake Kongslie 2022-04-23T05:43:36Z urn:sha1:1aa35d02a3675a2da94f264364681ee7b71111fb Transmit two stop bits to RS232 uart. 2022-04-23T05:43:10Z Julian Blake Kongslie 2022-04-23T05:43:10Z urn:sha1:ac61ee2ad230b8f93a23c9cfe01880b4385fd747