multipdp8/hdl, branch main Unnamed repository; edit this file 'description' to name the repository. https://git.jblake.org/multipdp8/atom?h=main 2022-07-24T21:59:03Z Writeback cache using explicit altsyncram instead of inferred memory. 2022-07-24T21:59:03Z Julian Blake Kongslie 2022-07-24T21:59:03Z urn:sha1:1aeb760d093189486efbf5adf3292881eda94eb0 Rename memory message types for more clarity. 2022-07-10T21:23:22Z Julian Blake Kongslie 2022-07-10T21:23:22Z urn:sha1:641151b7123c4e5dbbb95392f65c0f3960fc0fef Add cache clearing to the command parser. 2022-06-05T23:23:07Z Julian Blake Kongslie 2022-06-05T23:23:07Z urn:sha1:83eb76e0b3f6570b5e27e2295551f648eea96d86 Working L1 cache. 2022-06-05T22:42:26Z Julian Blake Kongslie 2022-06-05T22:34:23Z urn:sha1:9ce65b7d3573d92e1d98a13b58a5d5763ba073c5 Add support for bulk memory dumping to command parser. 2022-05-29T23:38:00Z Julian Blake Kongslie 2022-05-29T23:38:00Z urn:sha1:3e5a998a2cb380d90615b524b5e41c671ab8004d Single-cycle bypass when there is no contention on memory arbiter. 2022-05-29T23:33:56Z Julian Blake Kongslie 2022-05-29T23:33:56Z urn:sha1:fd8f6b112a8a7545d58d1c6974c1214b85252709 Only run selector logic if we need a new selection next cycle. 2022-05-29T23:33:24Z Julian Blake Kongslie 2022-05-29T23:33:24Z urn:sha1:28d7b77b927144d69a82d8eaec6dc65c8afc5626 Two-cycle memory arbiter, enabling 16 PDP-8s @ 50MHz. 2022-05-23T00:09:03Z Julian Blake Kongslie 2022-05-23T00:09:03Z urn:sha1:085e5ceac41833f197c6cebda1c0ec925c59fb8b Only sample RS232 signals once per clock; use a delayed flop internally. 2022-05-22T22:42:55Z Julian Blake Kongslie 2022-05-22T22:42:55Z urn:sha1:d6d6edfd57c3dc4db01666034d11ac84d31ec2ef This removes metastability issues on inputs and makes everything work. Fix the RS232 receive state machine 😠💢:mad: 2022-05-15T22:53:36Z Julian Blake Kongslie 2022-05-15T22:53:36Z urn:sha1:716ed41a46aea2a3c81564b6e6a55e3b3e43ec46 Our current consensus is that we have a bug which causes the RX state machine to make incomprehensible jumps when the sample counter is more than about 9 bits wide. We haven't completely pinned down the problem; we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter. I hate Verilog and Altera, both exclusively and in combination.