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<updated>2022-06-05T22:42:26Z</updated>
<entry>
<title>Working L1 cache.</title>
<updated>2022-06-05T22:42:26Z</updated>
<author>
<name>Julian Blake Kongslie</name>
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<published>2022-06-05T22:34:23Z</published>
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<entry>
<title>Consistent RS232 wire names (DCE side names is used everywhere)</title>
<updated>2022-05-15T22:50:21Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-05-15T22:50:21Z</published>
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<entry>
<title>*Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.</title>
<updated>2022-05-08T22:51:35Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-05-08T22:51:35Z</published>
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<entry>
<title>Working (but very slow) RS232 UART</title>
<updated>2022-04-17T22:58:55Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-04-17T22:57:29Z</published>
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<entry>
<title>Add RX/TX/RTS/CTS pin assignments for future RS232 work.</title>
<updated>2022-03-28T00:00:11Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-03-28T00:00:11Z</published>
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<entry>
<title>Add a clock output pin for debugging the PLL.</title>
<updated>2022-03-27T23:59:18Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-03-27T23:59:18Z</published>
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<entry>
<title>Initial commit.</title>
<updated>2022-02-28T01:21:05Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2022-02-28T01:21:05Z</published>
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