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authorJulian Blake Kongslie2022-02-27 17:21:05 -0800
committerJulian Blake Kongslie2022-02-27 17:21:05 -0800
commit0553c4839c06011bd044f69b4913e5c793fdd2ec (patch)
treed11e69863532621fe1fa55cc7e8aa2a8cfa3b727 /altera/clocks.sdc
downloadmultipdp8-0553c4839c06011bd044f69b4913e5c793fdd2ec.tar.xz
Initial commit.
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diff --git a/altera/clocks.sdc b/altera/clocks.sdc
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1# This is the clock for timing analysis, not timing-driven synthesis.
2# See init.tcl for the other clock.
3create_clock -period "50 MHz" clock