Don't use SystemVerilog parametric types because Altera doesn't support them.

1 files changed, 9 insertions, 9 deletions

diff --git a/hdl/fifo.sv b/hdl/fifo.sv
index 4158067..a067914 100644
--- a/hdl/fifo.sv
+++ b/hdl/fifo.sv
@@ -1,23 +1,23 @@
 module fifo
-    #(  type    data_t  = bit
-
-    ,           DEPTH_BITS  = 10
+    #(  WIDTH_BITS  = 1
+    ,   DEPTH_BITS  = 10
     )
     (   input   bit     clock_in
     ,   input   bit     clock_out
     ,   input   bit     reset
 
-    ,   output  bit     in_ready
-    ,   input   bit     in_valid
-    ,   input   data_t  in_data
+    ,   output  bit                     in_ready
+    ,   input   bit                     in_valid
+    ,   input   bit [WIDTH_BITS-1:0]    in_data
 
-    ,   input   bit     out_ready
-    ,   output  bit     out_valid
-    ,   output  data_t  out_data
+    ,   input   bit                     out_ready
+    ,   output  bit                     out_valid
+    ,   output  bit [WIDTH_BITS-1:0]    out_data
     );
 
     localparam  DEPTH   = 1<<DEPTH_BITS;
 
+    typedef bit [WIDTH_BITS-1:0]    data_t;
     typedef bit [DEPTH_BITS-1:0]    addr_t;
 
     data_t  data    [DEPTH-1:0];