Add cache clearing to the command parser.

1 files changed, 10 insertions, 5 deletions

diff --git a/hdl/mem_cache.sv b/hdl/mem_cache.sv
index 5f3db73..2257a4f 100644
--- a/hdl/mem_cache.sv
+++ b/hdl/mem_cache.sv
@@ -6,6 +6,8 @@ module mem_cache
     (   input   bit clock
     ,   input   bit reset
 
+    ,   input   bit clear
+
     ,   output  bit             core_command_ready
     ,   input   bit             core_command_valid
     ,   input   pdp_command_t   core_command_data
@@ -52,16 +54,19 @@ module mem_cache
             core_response_valid = 0;
             outstanding_fill = 0;
             reset_entry = 0;
-        end else if (reset_entry < (1<<SET_BITS)) begin
-            cache[reset_entry] = 0;
-            ++reset_entry;
         end else begin
+            if (clear)
+                reset_entry = 0;
+
             if (ram_command_ready && ram_command_valid)
                 ram_command_valid = 0;
             if (core_response_ready && core_response_valid)
                 core_response_valid = 0;
 
-            if (ram_response_ready && ram_response_valid) begin
+            if (!outstanding_fill && !reset_entry[SET_BITS]) begin
+                cache[reset_entry[SET_BITS-1:0]] = 0;
+                ++reset_entry;
+            end else if (ram_response_ready && ram_response_valid && outstanding_fill) begin
                 automatic address_tag_t tag;
                 automatic set_t set;
                 automatic cache_entry_t entry;
@@ -100,7 +105,7 @@ module mem_cache
                 end
             end
 
-            core_command_ready = !ram_command_valid && !core_response_valid && !outstanding_fill;
+            core_command_ready = reset_entry[SET_BITS] && !ram_command_valid && !core_response_valid && !outstanding_fill;
             ram_response_ready = !core_response_valid;
         end
     end