Initial commit.

1 files changed, 126 insertions, 0 deletions

diff --git a/hdl/pll.sv b/hdl/pll.sv
new file mode 100644
index 0000000..d348b7c
--- /dev/null
+++ b/hdl/pll.sv
@@ -0,0 +1,126 @@
+module pll
+    #(  MULTIPLY_BY = 1
+    ,   DIVIDE_BY   = 1
+    ,   NATIVE_PERIOD_PICOSECONDS = 20_000
+    )
+    (   input   bit native_clk
+    ,   input   bit reset_n
+
+    ,   output  bit target_clk
+    ,   output  bit reset
+    );
+
+enum
+    {   NOT_LOCKED
+    ,   RESET_CYCLE
+    ,   READY
+    } state = state.first;
+
+bit locked;
+
+`ifndef SYNTHESIS
+
+assign target_clk = native_clk;
+assign locked = 1;
+
+`else
+
+altpll
+    #(  .clk0_divide_by(DIVIDE_BY)
+    ,   .clk0_multiply_by(MULTIPLY_BY)
+    ,   .inclk0_input_frequency(NATIVE_PERIOD_PICOSECONDS)
+    ,   .intended_device_family("Cyclone 10 LP")
+    ,   .operation_mode("NORMAL")
+    ,   .port_activeclock("PORT_UNUSED")
+    ,   .port_areset("PORT_USED")
+    ,   .port_clkbad0("PORT_UNUSED")
+    ,   .port_clkbad1("PORT_UNUSED")
+    ,   .port_clkloss("PORT_UNUSED")
+    ,   .port_clkswitch("PORT_UNUSED")
+    ,   .port_configupdate("PORT_UNUSED")
+    ,   .port_fbin("PORT_UNUSED")
+    ,   .port_inclk0("PORT_USED")
+    ,   .port_inclk1("PORT_UNUSED")
+    ,   .port_locked("PORT_USED")
+    ,   .port_pfdena("PORT_UNUSED")
+    ,   .port_phasecounterselect("PORT_UNUSED")
+    ,   .port_phasedone("PORT_UNUSED")
+    ,   .port_phasestep("PORT_UNUSED")
+    ,   .port_phaseupdown("PORT_UNUSED")
+    ,   .port_pllena("PORT_UNUSED")
+    ,   .port_scanaclr("PORT_UNUSED")
+    ,   .port_scanclk("PORT_UNUSED")
+    ,   .port_scanclkena("PORT_UNUSED")
+    ,   .port_scandata("PORT_UNUSED")
+    ,   .port_scandataout("PORT_UNUSED")
+    ,   .port_scandone("PORT_UNUSED")
+    ,   .port_scanread("PORT_UNUSED")
+    ,   .port_scanwrite("PORT_UNUSED")
+    ,   .port_clk0("PORT_USED")
+    ,   .port_clk1("PORT_UNUSED")
+    ,   .port_clk2("PORT_UNUSED")
+    ,   .port_clk3("PORT_UNUSED")
+    ,   .port_clk4("PORT_UNUSED")
+    ,   .port_clk5("PORT_UNUSED")
+    ,   .port_clkena0("PORT_UNUSED")
+    ,   .port_clkena1("PORT_UNUSED")
+    ,   .port_clkena2("PORT_UNUSED")
+    ,   .port_clkena3("PORT_UNUSED")
+    ,   .port_clkena4("PORT_UNUSED")
+    ,   .port_clkena5("PORT_UNUSED")
+    ,   .port_extclk0("PORT_UNUSED")
+    ,   .port_extclk1("PORT_UNUSED")
+    ,   .port_extclk2("PORT_UNUSED")
+    ,   .port_extclk3("PORT_UNUSED")
+    ,   .self_reset_on_loss_lock("ON")
+    ,   .width_clock(5)
+    ) pll
+    (   .areset(!reset_n)
+    ,   .inclk(native_clk)
+    ,   .clk(target_clk)
+    ,   .locked(locked)
+    ,   .activeclock()
+    ,   .clkbad()
+    ,   .clkena({6{1'b1}})
+    ,   .clkloss()
+    ,   .clkswitch(1'b0)
+    ,   .configupdate(1'b0)
+    ,   .extclkena({4{1'b1}})
+    ,   .fbin(1'b1)
+    ,   .fbmimicbidir()
+    ,   .fbout()
+    ,   .fref()
+    ,   .icdrclk()
+    ,   .pfdena(1'b1)
+    ,   .phasecounterselect({4{1'b1}})
+    ,   .phasedone()
+    ,   .phasestep(1'b1)
+    ,   .phaseupdown(1'b1)
+    ,   .pllena(1'b1)
+    ,   .scanaclr(1'b0)
+    ,   .scanclk(1'b0)
+    ,   .scanclkena(1'b1)
+    ,   .scandata(1'b0)
+    ,   .scandataout()
+    ,   .scandone()
+    ,   .scanread(1'b0)
+    ,   .scanwrite(1'b0)
+    ,   .sclkout0()
+    ,   .sclkout1()
+    ,   .vcooverrange()
+    ,   .vcounderrange()
+    );
+
+`endif
+
+always_ff @(posedge target_clk) begin
+    if (!reset_n || !locked) begin
+        state = state.first;
+    end else if (state != state.last) begin
+        state = state.next;
+    end
+
+    reset = !(state == state.last);
+end
+
+endmodule