Minor paranoia about ensuring that we're in the correct half_state

coming out of t_rwr delay between memory transactions

1 files changed, 1 insertions, 0 deletions

diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 8922a09..14a1609 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -129,6 +129,7 @@ module ram_controller
                 ram_data_oe = 0;
                 ram_csn = 1;
                 ram_clkp = 0;
+                half_state = half_state.first;
                 if (trwr_counter != 0) --trwr_counter;
             end else if (half_state == TOGGLE_CLOCK) begin
                 half_state = half_state.next;