summaryrefslogtreecommitdiff
path: root/hdl
diff options
context:
space:
mode:
authorJulian Blake Kongslie2022-05-08 15:51:35 -0700
committerJulian Blake Kongslie2022-05-08 15:51:35 -0700
commit38c5ae5b60eae9562b97da42f47af3861847f8e5 (patch)
tree556fd9e5c38fb2feea56ce5741ca02a5e110ad63 /hdl
parentMake the script for setting up the TTY actually connect. (diff)
downloadmultipdp8-38c5ae5b60eae9562b97da42f47af3861847f8e5.tar.xz
*Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.
Diffstat (limited to '')
-rw-r--r--hdl/core.sv2
-rw-r--r--hdl/rs232.sv109
-rw-r--r--hdl/top.sv118
3 files changed, 133 insertions, 96 deletions
diff --git a/hdl/core.sv b/hdl/core.sv
index 6827b8e..587ffeb 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -3,8 +3,6 @@
3`define DATA_BITS 12 3`define DATA_BITS 12
4 4
5module core 5module core
6 #( JTAG_INSTANCE = 1
7 )
8 ( input bit clk 6 ( input bit clk
9 , input bit reset 7 , input bit reset
10 8
diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 31beb1e..ef53f12 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -1,6 +1,9 @@
1`include "defs.svh" 1`include "defs.svh"
2 2
3module rs232_tx 3module rs232_tx
4 #( PARITY = 0
5 , STOP_BITS = 2
6 )
4 ( input bit clock 7 ( input bit clock
5 , input bit reset 8 , input bit reset
6 9
@@ -9,6 +12,7 @@ module rs232_tx
9 , input uart_byte_t out_data 12 , input uart_byte_t out_data
10 13
11 , output bit tx 14 , output bit tx
15 , input bit cts
12 ); 16 );
13 17
14 bit hold_valid; 18 bit hold_valid;
@@ -18,40 +22,45 @@ module rs232_tx
18 (* syn_encoding = "one-hot" *) enum int unsigned 22 (* syn_encoding = "one-hot" *) enum int unsigned
19 { START 23 { START
20 , DATA 24 , DATA
21 , PARITY 25 , PARITY_BIT
22 , STOP1 26 , STOP
23 , STOP2
24 } state; 27 } state;
25 28
26 bit [$clog2(`UART_BYTE_BITS):0] data_bits; 29 bit [$clog2($bits(uart_byte_t)):0] data_bits;
30 bit [$clog2(STOP_BITS):0] stop_bits;
27 31
28 always @(posedge clock, posedge reset) begin 32 always @(posedge clock, posedge reset) begin
29 if (reset) begin 33 if (reset) begin
30 out_ready = 0; 34 out_ready = 0;
31 tx = 1; 35 tx = 1;
32 hold_valid = 0; 36 hold_valid = 0;
33 parity = 0; 37 parity = PARITY;
34 state = state.first; 38 state = state.first;
35 data_bits = 0; 39 data_bits = 0;
40 stop_bits = 0;
36 end else begin 41 end else begin
37 if (out_ready && out_valid) begin 42 if (out_ready && out_valid) begin
38 hold_valid = 1; 43 hold_valid = 1;
39 hold = out_data; 44 hold = out_data;
40 parity = 0; 45 parity = PARITY;
41 state = state.first; 46 state = state.first;
42 data_bits = 0; 47 data_bits = 0;
48 stop_bits = 0;
43 end 49 end
44 50
45 if (hold_valid) begin 51 if (hold_valid) begin
46 case (state) 52 case (state)
47 53
48 START: begin 54 START: begin
49 tx = 0; 55 if (!cts) begin
50 state = state.next; 56 tx = 0;
57 state = state.next;
58 end
51 end 59 end
52 60
53 DATA: begin 61 DATA: begin
54 tx = hold[data_bits]; 62 tx = hold[0];
63 hold = hold >> 1;
55 parity = parity ^ tx; 64 parity = parity ^ tx;
56 if (data_bits == `UART_BYTE_BITS-1) 65 if (data_bits == `UART_BYTE_BITS-1)
57 state = state.next; 66 state = state.next;
@@ -59,20 +68,19 @@ module rs232_tx
59 ++data_bits; 68 ++data_bits;
60 end 69 end
61 70
62 PARITY: begin 71 PARITY_BIT: begin
63 tx = parity; 72 tx = parity;
64 state = state.next; 73 state = state.next;
65 end 74 end
66 75
67 STOP1: begin 76 STOP: begin
68 tx = 1;
69 state = state.next;
70 end
71
72 STOP2: begin
73 hold_valid = 0;
74 tx = 1; 77 tx = 1;
75 state = state.next; 78 if (stop_bits == STOP_BITS-1) begin
79 hold_valid = 0;
80 state = state.next;
81 end else begin
82 ++stop_bits;
83 end
76 end 84 end
77 85
78 endcase 86 endcase
@@ -87,69 +95,94 @@ module rs232_tx
87endmodule 95endmodule
88 96
89module rs232_rx 97module rs232_rx
90 #( OVERSAMPLE = 0 98 #( PARITY = 0
99 , OVERSAMPLE = 0
91 ) 100 )
92 ( input bit clock 101 ( input bit clock
93 , input bit reset 102 , input bit reset
94 103
104 , output bit clock_out
105
95 , input bit in_ready 106 , input bit in_ready
96 , output bit in_valid 107 , output bit in_valid
97 , output uart_byte_t in_data 108 , output uart_byte_t in_data
98 109
99 , input bit rx 110 , input bit rx
111 , output bit rts
100 ); 112 );
101 113
102 (* syn_encoding = "one-hot" *) enum int unsigned 114 (* syn_encoding = "one-hot" *) enum int unsigned
103 { START 115 { START
116 , ALIGN
104 , DATA 117 , DATA
105 , PARITY 118 , PARITY_BIT
106 , STOP 119 , STOP
120 , REALSTOP
107 } state; 121 } state;
108 122
109 uart_byte_t buffer; 123 uart_byte_t buffer;
110 bit [$clog2(`UART_BYTE_BITS):0] data_bits; 124 bit [$clog2(`UART_BYTE_BITS):0] data_bits;
111 bit parity; 125 bit parity;
112 126
113 bit [$clog2(OVERSAMPLE+1):0] sample; 127 bit [$clog2(OVERSAMPLE+1)+2:0] sample;
128 bit [$clog2(OVERSAMPLE+1):0] clock_counter;
114 129
115 always @(posedge clock, posedge reset) begin 130 always @(posedge clock, posedge reset) begin
116 if (reset) begin 131 if (reset) begin
132 clock_out = 0;
117 in_valid = 0; 133 in_valid = 0;
134 rts = 1;
118 state = state.first; 135 state = state.first;
119 buffer = 0; 136 buffer = 0;
120 data_bits = 0; 137 data_bits = 0;
121 parity = 0; 138 parity = PARITY;
122 sample = 0; 139 sample = 0;
140 clock_counter = 0;
123 end else begin 141 end else begin
124 automatic bit ok = 0; 142 automatic bit ok = 0;
125 143
126 if (in_ready && in_valid) 144 if (in_ready && in_valid)
127 in_valid = 0; 145 in_valid = 0;
128 146
129 if (state == state.first) begin 147 if (state == state.first || state == state.last) begin
148 sample = 0;
130 ok = 1; 149 ok = 1;
131 end else begin 150 end else begin
132 ++sample; 151 ++sample;
133 if (sample == OVERSAMPLE+1) begin 152 if (sample > OVERSAMPLE) begin
134 sample = 0; 153 sample = 0;
135 ok = 1; 154 ok = 1;
136 end 155 end
137 end 156 end
138 157
158 ++clock_counter;
159 if (clock_counter > OVERSAMPLE) begin
160 clock_out = 1;
161 clock_counter = 0;
162 end else begin
163 clock_out = 0;
164 end
165
139 if (ok) begin 166 if (ok) begin
140 case (state) 167 case (state)
141 168
142 START: begin 169 START: begin
143 if (rx == 0) begin 170 if (rx == 0) begin
144 state = state.next; 171 state = state.next;
172 if (OVERSAMPLE == 0)
173 state = state.next;
174 sample = (OVERSAMPLE+1) / 2;
145 buffer = 0; 175 buffer = 0;
146 data_bits = 0; 176 data_bits = 0;
147 parity = 0; 177 parity = PARITY;
148 end 178 end
149 end 179 end
150 180
181 ALIGN: state = state.next;
182
151 DATA: begin 183 DATA: begin
152 buffer[data_bits] = rx; 184 buffer = buffer >> 1;
185 buffer[`UART_BYTE_BITS-1] = rx;
153 parity = parity ^ rx; 186 parity = parity ^ rx;
154 if (data_bits == `UART_BYTE_BITS-1) 187 if (data_bits == `UART_BYTE_BITS-1)
155 state = state.next; 188 state = state.next;
@@ -157,24 +190,34 @@ module rs232_rx
157 ++data_bits; 190 ++data_bits;
158 end 191 end
159 192
160 PARITY: begin 193 PARITY_BIT: begin
161 parity = parity ^ rx; 194 parity = parity ^ rx;
162 if (parity == 0) 195 state = state.next;
163 state = state.next;
164 else
165 state = state.first;
166 end 196 end
167 197
168 STOP: begin 198 STOP: begin
169 if (!in_valid && rx == 1) begin 199 if (!in_valid && rx == 1 && parity == 0) begin
170 in_valid = 1; 200 in_valid = 1;
171 in_data = buffer; 201 in_data = buffer;
172 end 202 end
173 state = state.next; 203 if (rx == 1 && parity == 0) begin
204 clock_counter = (OVERSAMPLE+1)/2;
205 end
206 if (rx == 1)
207 state = state.first;
208 else
209 state = state.next;
210 end
211
212 REALSTOP: begin
213 if (rx == 1)
214 state = state.first;
174 end 215 end
175 216
176 endcase 217 endcase
177 end 218 end
219
220 rts = !(state == state.first && !in_valid);
178 end 221 end
179 end 222 end
180 223
diff --git a/hdl/top.sv b/hdl/top.sv
index ffe6656..6512185 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -7,10 +7,14 @@ module top
7 , inout wire [10:1] gpioa 7 , inout wire [10:1] gpioa
8 , inout wire [28:13] gpiob 8 , inout wire [28:13] gpiob
9 , inout wire [40:31] gpioc 9 , inout wire [40:31] gpioc
10 , output wire clock_out
11 10
12 , output wire rs232_tx 11 , output wire rs232_tx
13 , input wire rs232_rx 12 , input wire rs232_rx
13 , output wire rs232_rts
14 , input wire rs232_cts
15
16 , output wire debug_tx
17 , output wire debug_rx
14 18
15 , output bit ram_resetn 19 , output bit ram_resetn
16 , output bit ram_csn 20 , output bit ram_csn
@@ -20,11 +24,14 @@ module top
20 , inout bit [7:0] ram_data 24 , inout bit [7:0] ram_data
21 ); 25 );
22 26
27 assign debug_tx = rs232_tx;
28 assign debug_rx = rs232_rx;
29
23 bit internal_clock; 30 bit internal_clock;
24 bit internal_reset; 31 bit internal_reset;
25 pll 32 pll
26 #( .MULTIPLY_BY(3) 33 #( .MULTIPLY_BY(1)
27 , .DIVIDE_BY(5) 34 , .DIVIDE_BY(1)
28 ) fastpll 35 ) fastpll
29 ( .native_clk(clock) 36 ( .native_clk(clock)
30 , .reset_n(resetn) 37 , .reset_n(resetn)
@@ -32,51 +39,36 @@ module top
32 , .reset(internal_reset) 39 , .reset(internal_reset)
33 ); 40 );
34 41
35 //assign clock_out = internal_clock; 42 bit rs232_tx_clock;
36 43 bit rs232_tx_reset = 1;
37 bit rs232_tx_clock = 0; 44 always @(posedge rs232_tx_clock) begin
38 bit [17:0] rs232_tx_div = 0;
39 always @(posedge internal_clock) begin
40 if (internal_reset) begin 45 if (internal_reset) begin
41 rs232_tx_clock = 0; 46 rs232_tx_reset = 1;
42 rs232_tx_div = 0;
43 end else begin 47 end else begin
44 if (++rs232_tx_div == 130) begin // (30MHz/2)/115200 48 rs232_tx_reset = 0;
45 ++rs232_tx_clock;
46 rs232_tx_div = 0;
47 end
48 end 49 end
49 end 50 end
50 51
51 assign clock_out = rs232_tx_clock; 52 bit rs232_rx_clock;
52 53 assign rs232_rx_clock = internal_clock;
53 bit rs232_rx_clock = 0;
54 bit [4:0] rs232_rx_div = 0;
55 always @(posedge internal_clock) begin
56 if (internal_reset) begin
57 rs232_rx_clock = 0;
58 rs232_rx_div = 0;
59 end else begin
60 if (++rs232_rx_div == 16) begin // (30MHz/2)/(115200*8)
61 ++rs232_rx_clock;
62 rs232_rx_div = 0;
63 end
64 end
65 end
66 54
67 bit wire_tx_ready; 55 bit wire_tx_ready;
68 bit wire_tx_valid; 56 bit wire_tx_valid;
69 uart_byte_t wire_tx_data; 57 uart_byte_t wire_tx_data;
70 58
71 rs232_tx wiretx 59 rs232_tx
60 #( .PARITY(1)
61 , .STOP_BITS(2)
62 ) wiretx
72 ( .clock(rs232_tx_clock) 63 ( .clock(rs232_tx_clock)
73 , .reset(internal_reset) 64 , .reset(rs232_tx_reset)
74 65
75 , .out_ready(wire_tx_ready) 66 , .out_ready(wire_tx_ready)
76 , .out_valid(wire_tx_valid) 67 , .out_valid(wire_tx_valid)
77 , .out_data(wire_tx_data) 68 , .out_data(wire_tx_data)
78 69
79 , .tx(rs232_tx) 70 , .tx(rs232_tx)
71 , .cts(rs232_cts)
80 ); 72 );
81 73
82 bit rs232_tx_ready; 74 bit rs232_tx_ready;
@@ -88,6 +80,7 @@ module top
88 ) fifotx 80 ) fifotx
89 ( .clock_in(internal_clock) 81 ( .clock_in(internal_clock)
90 , .clock_out(rs232_tx_clock) 82 , .clock_out(rs232_tx_clock)
83 , .reset(internal_reset || rs232_tx_reset)
91 84
92 , .in_ready(rs232_tx_ready) 85 , .in_ready(rs232_tx_ready)
93 , .in_valid(rs232_tx_valid) 86 , .in_valid(rs232_tx_valid)
@@ -103,16 +96,20 @@ module top
103 uart_byte_t wire_rx_data; 96 uart_byte_t wire_rx_data;
104 97
105 rs232_rx 98 rs232_rx
106 #( .OVERSAMPLE(7) 99 #( .PARITY(1)
100 , .OVERSAMPLE(433)
107 ) wirerx 101 ) wirerx
108 ( .clock(rs232_rx_clock) 102 ( .clock(rs232_rx_clock)
109 , .reset(internal_reset) 103 , .reset(internal_reset)
110 104
105 , .clock_out(rs232_tx_clock)
106
111 , .in_ready(wire_rx_ready) 107 , .in_ready(wire_rx_ready)
112 , .in_valid(wire_rx_valid) 108 , .in_valid(wire_rx_valid)
113 , .in_data(wire_rx_data) 109 , .in_data(wire_rx_data)
114 110
115 , .rx(rs232_rx) 111 , .rx(rs232_rx)
112 , .rts(rs232_rts)
116 ); 113 );
117 114
118 bit rs232_rx_ready; 115 bit rs232_rx_ready;
@@ -122,8 +119,9 @@ module top
122 fifo 119 fifo
123 #( .WIDTH_BITS($bits(uart_byte_t)) 120 #( .WIDTH_BITS($bits(uart_byte_t))
124 ) fiforx 121 ) fiforx
125 ( .clock_in(rs232_clock) 122 ( .clock_in(rs232_rx_clock)
126 , .clock_out(internal_clock) 123 , .clock_out(internal_clock)
124 , .reset(internal_reset)
127 125
128 , .in_ready(wire_rx_ready) 126 , .in_ready(wire_rx_ready)
129 , .in_valid(wire_rx_valid) 127 , .in_valid(wire_rx_valid)
@@ -182,6 +180,7 @@ module top
182 bit [7:0] ram_data_out; 180 bit [7:0] ram_data_out;
183 assign ram_data = ram_data_oe ? ram_data_out : 8'bZ; 181 assign ram_data = ram_data_oe ? ram_data_out : 8'bZ;
184 182
183/*
185 alt_jtag_atlantic 184 alt_jtag_atlantic
186 #( .INSTANCE_ID(0) 185 #( .INSTANCE_ID(0)
187 , .LOG2_RXFIFO_DEPTH(10) 186 , .LOG2_RXFIFO_DEPTH(10)
@@ -199,6 +198,15 @@ module top
199 , .t_dav(ram_rx_ready) 198 , .t_dav(ram_rx_ready)
200 , .t_ena(ram_rx_valid) 199 , .t_ena(ram_rx_valid)
201 ); 200 );
201*/
202
203 assign ram_tx_ready = rs232_tx_ready;
204 assign rs232_tx_valid = ram_tx_valid;
205 assign rs232_tx_data = ram_tx_data;
206
207 assign rs232_rx_ready = ram_rx_ready;
208 assign ram_rx_valid = rs232_rx_valid;
209 assign ram_rx_data = rs232_rx_data;
202 210
203 echo_arbiter uart0arb 211 echo_arbiter uart0arb
204 ( .clock(internal_clock) 212 ( .clock(internal_clock)
@@ -445,9 +453,7 @@ module top
445 bit rx_valid; 453 bit rx_valid;
446 uart_byte_t rx_data; 454 uart_byte_t rx_data;
447 455
448 core 456 core cpu
449 #( .JTAG_INSTANCE(1+i)
450 ) cpu
451 ( .clk(internal_clock) 457 ( .clk(internal_clock)
452 , .reset(internal_reset) 458 , .reset(internal_reset)
453 459
@@ -507,33 +513,23 @@ module top
507 , .led_link(local_led_link[i]) 513 , .led_link(local_led_link[i])
508 ); 514 );
509 515
510 if (i == `NUM_PDPS-1) begin 516 alt_jtag_atlantic
511 assign tx_ready = rs232_tx_ready; 517 #( .INSTANCE_ID(i)
512 assign rs232_tx_valid = tx_valid; 518 , .LOG2_RXFIFO_DEPTH(10)
513 assign rs232_tx_data = tx_data; 519 , .LOG2_TXFIFO_DEPTH(10)
514 520 , .SLD_AUTO_INSTANCE_INDEX("NO")
515 assign rs232_rx_ready = rx_ready; 521 ) uart
516 assign rx_valid = rs232_rx_valid; 522 ( .clk(internal_clock)
517 assign rx_data = rs232_rx_data; 523 , .rst_n(!internal_reset)
518 end else begin
519 alt_jtag_atlantic
520 #( .INSTANCE_ID(1+i)
521 , .LOG2_RXFIFO_DEPTH(10)
522 , .LOG2_TXFIFO_DEPTH(10)
523 , .SLD_AUTO_INSTANCE_INDEX("NO")
524 ) uart
525 ( .clk(internal_clock)
526 , .rst_n(!internal_reset)
527 524
528 , .r_dat(tx_data) 525 , .r_dat(tx_data)
529 , .r_val(tx_valid) 526 , .r_val(tx_valid)
530 , .r_ena(tx_ready) 527 , .r_ena(tx_ready)
531 528
532 , .t_dat(rx_data) 529 , .t_dat(rx_data)
533 , .t_dav(rx_ready) 530 , .t_dav(rx_ready)
534 , .t_ena(rx_valid) 531 , .t_ena(rx_valid)
535 ); 532 );
536 end
537 533
538 end 534 end
539 535
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-19 01:03:06 -0700