Add cache clearing to the command parser.

3 files changed, 24 insertions, 5 deletions

diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv
index 1520db4..a4a5190 100644
--- a/hdl/command_parser.sv
+++ b/hdl/command_parser.sv
@@ -20,6 +20,8 @@ module command_parser
     ,   input   bit loop_ready
     ,   output  bit loop_valid
     ,   output  bit loop_data
+
+    ,   output  bit clear_caches
     );
 
     bit         input_byte_valid;
@@ -43,6 +45,7 @@ module command_parser
                 command_data.mask[i] = ~0;
             command_data.tag = TAG;
             loop_valid = 0;
+            clear_caches = 0;
             input_byte_valid = 0;
             input_byte = 0;
             loop_count = 0;
@@ -62,6 +65,7 @@ module command_parser
             if (loop_ready && loop_valid) begin
                 loop_valid = 0;
             end
+            clear_caches = 0;
 
             if (!command_valid && !loop_valid) begin
                 case (state)
@@ -106,6 +110,10 @@ module command_parser
                         state = READ_LOOP_COUNT;
                     end
 
+                    "$": begin
+                        clear_caches = 1;
+                    end
+
                     endcase
                     input_byte_valid = 0;
                 end
diff --git a/hdl/mem_cache.sv b/hdl/mem_cache.sv
index 5f3db73..2257a4f 100644
--- a/hdl/mem_cache.sv
+++ b/hdl/mem_cache.sv
@@ -6,6 +6,8 @@ module mem_cache
     (   input   bit clock
     ,   input   bit reset
 
+    ,   input   bit clear
+
     ,   output  bit             core_command_ready
     ,   input   bit             core_command_valid
     ,   input   pdp_command_t   core_command_data
@@ -52,16 +54,19 @@ module mem_cache
             core_response_valid = 0;
             outstanding_fill = 0;
             reset_entry = 0;
-        end else if (reset_entry < (1<<SET_BITS)) begin
-            cache[reset_entry] = 0;
-            ++reset_entry;
         end else begin
+            if (clear)
+                reset_entry = 0;
+
             if (ram_command_ready && ram_command_valid)
                 ram_command_valid = 0;
             if (core_response_ready && core_response_valid)
                 core_response_valid = 0;
 
-            if (ram_response_ready && ram_response_valid) begin
+            if (!outstanding_fill && !reset_entry[SET_BITS]) begin
+                cache[reset_entry[SET_BITS-1:0]] = 0;
+                ++reset_entry;
+            end else if (ram_response_ready && ram_response_valid && outstanding_fill) begin
                 automatic address_tag_t tag;
                 automatic set_t set;
                 automatic cache_entry_t entry;
@@ -100,7 +105,7 @@ module mem_cache
                 end
             end
 
-            core_command_ready = !ram_command_valid && !core_response_valid && !outstanding_fill;
+            core_command_ready = reset_entry[SET_BITS] && !ram_command_valid && !core_response_valid && !outstanding_fill;
             ram_response_ready = !core_response_valid;
         end
     end
diff --git a/hdl/top.sv b/hdl/top.sv
index 26006be..5f98ff9 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -234,6 +234,8 @@ module top
         ,   .out_data(ram_tx_data)
         );
 
+    bit clear_caches;
+
     command_parser parser
         (   .clock(internal_clock)
         ,   .reset(internal_reset)
@@ -253,6 +255,8 @@ module top
         ,   .loop_ready(loop_ready)
         ,   .loop_valid(loop_valid)
         ,   .loop_data(loop_data)
+
+        ,   .clear_caches(clear_caches)
         );
 
     mem_arbiter memarb
@@ -491,6 +495,8 @@ module top
                 (   .clock(internal_clock)
                 ,   .reset(internal_reset)
 
+                ,   .clear(clear_caches)
+
                 ,   .core_command_ready(cache_command_ready)
                 ,   .core_command_valid(cache_command_valid)
                 ,   .core_command_data(cache_command_data)