diff options
Diffstat (limited to '')
| -rw-r--r-- | hdl/echo_arbiter.sv | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/hdl/echo_arbiter.sv b/hdl/echo_arbiter.sv new file mode 100644 index 0000000..1c27e31 --- /dev/null +++ b/hdl/echo_arbiter.sv | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | `include "defs.svh" | ||
| 2 | |||
| 3 | module echo_arbiter | ||
| 4 | ( input bit clock | ||
| 5 | , input bit reset | ||
| 6 | |||
| 7 | , output bit in0_ready | ||
| 8 | , input bit in0_valid | ||
| 9 | , input uart_byte_t in0_data | ||
| 10 | |||
| 11 | , output bit in1_ready | ||
| 12 | , input bit in1_valid | ||
| 13 | , input uart_byte_t in1_data | ||
| 14 | |||
| 15 | , input bit out_ready | ||
| 16 | , output bit out_valid | ||
| 17 | , output uart_byte_t out_data | ||
| 18 | ); | ||
| 19 | |||
| 20 | bit in0_hold_valid; | ||
| 21 | uart_byte_t in0_hold; | ||
| 22 | |||
| 23 | bit in1_hold_valid; | ||
| 24 | uart_byte_t in1_hold; | ||
| 25 | |||
| 26 | always @(posedge clock) begin | ||
| 27 | if (reset) begin | ||
| 28 | in0_ready = 0; | ||
| 29 | in1_ready = 0; | ||
| 30 | out_valid = 0; | ||
| 31 | out_data = 0; | ||
| 32 | in0_hold_valid = 0; | ||
| 33 | in0_hold = 0; | ||
| 34 | in1_hold_valid = 0; | ||
| 35 | in1_hold = 0; | ||
| 36 | end else begin | ||
| 37 | if (out_ready) out_valid = 0; | ||
| 38 | if (in0_ready && in0_valid) begin | ||
| 39 | in0_hold_valid = 1; | ||
| 40 | in0_hold = in0_data; | ||
| 41 | end | ||
| 42 | if (in1_ready && in1_valid) begin | ||
| 43 | in1_hold_valid = 1; | ||
| 44 | in1_hold = in1_data; | ||
| 45 | end | ||
| 46 | |||
| 47 | if (!out_valid) begin | ||
| 48 | if (in0_hold_valid) begin | ||
| 49 | out_valid = 1; | ||
| 50 | out_data = in0_hold; | ||
| 51 | in0_hold_valid = 0; | ||
| 52 | end else if (in1_hold_valid) begin | ||
| 53 | out_valid = 1; | ||
| 54 | out_data = in1_hold; | ||
| 55 | in1_hold_valid = 0; | ||
| 56 | end | ||
| 57 | end | ||
| 58 | |||
| 59 | in0_ready = !in0_hold_valid; | ||
| 60 | in1_ready = !in1_hold_valid; | ||
| 61 | end | ||
| 62 | end | ||
| 63 | |||
| 64 | endmodule | ||
