1 files changed, 4 insertions, 4 deletions
diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv
index 720699b..599be28 100644
--- a/hdl/mem_broadcast.sv
+++ b/hdl/mem_broadcast.sv
@@ -6,19 +6,19 @@ module mem_broadcast
    ,   output  bit                                 ram_ready
    ,   input   bit                                 ram_valid
-    ,   input   ram_read_response_t                 ram_data
+    ,   input   ram_to_arb_t                        ram_data
    ,   input   bit                                 print_ready
    ,   output  bit                                 print_valid
-    ,   output  ram_read_response_t                 print_data
+    ,   output  ram_to_arb_t                        print_data
    ,   input   bit                 [`NUM_PDPS-1:0] pdp_ready
    ,   output  bit                 [`NUM_PDPS-1:0] pdp_valid
-    ,   output  pdp_read_response_t [`NUM_PDPS-1:0] pdp_data
+    ,   output  mem_to_core_t       [`NUM_PDPS-1:0] pdp_data
    );
    bit                 hold_valid;
-    ram_read_response_t hold_data;
+    ram_to_arb_t        hold_data;
    always @(posedge clock) begin
        if (reset) begin

diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv index 720699b..599be28 100644 --- a/hdl/mem_broadcast.sv +++ b/hdl/mem_broadcast.sv
@@ -6,19 +6,19 @@ module mem_broadcast
6		6
7	, output bit ram_ready	7	, output bit ram_ready
8	, input bit ram_valid	8	, input bit ram_valid
9	, input ram_read_response_t ram_data	9	, input ram_to_arb_t ram_data
10		10
11	, input bit print_ready	11	, input bit print_ready
12	, output bit print_valid	12	, output bit print_valid
13	, output ram_read_response_t print_data	13	, output ram_to_arb_t print_data
14		14
15	, input bit [`NUM_PDPS-1:0] pdp_ready	15	, input bit [`NUM_PDPS-1:0] pdp_ready
16	, output bit [`NUM_PDPS-1:0] pdp_valid	16	, output bit [`NUM_PDPS-1:0] pdp_valid
17	, output pdp_read_response_t [`NUM_PDPS-1:0] pdp_data	17	, output mem_to_core_t [`NUM_PDPS-1:0] pdp_data
18	);	18	);
19		19
20	bit hold_valid;	20	bit hold_valid;
21	ram_read_response_t hold_data;	21	ram_to_arb_t hold_data;
22		22
23	always @(posedge clock) begin	23	always @(posedge clock) begin
24	if (reset) begin	24	if (reset) begin