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-rw-r--r--hdl/result_printer.sv71
1 files changed, 71 insertions, 0 deletions
diff --git a/hdl/result_printer.sv b/hdl/result_printer.sv
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1`include "defs.svh"
2
3module result_printer
4 #( TAG = 0
5 ) ( input bit clock
6 , input bit reset
7
8 , output bit result_ready
9 , input bit result_valid
10 , input ram_read_response_t result_data
11
12 , input bit echo_ready
13 , output bit echo_valid
14 , output uart_byte_t echo_data
15 );
16
17 ram_read_response_t hold;
18 ram_byte_count_t byte_count;
19 ram_word_count_t word_count;
20
21 (* syn_encoding = "one-hot" *) enum int unsigned
22 { HIGH_NIBBLE
23 , LOW_NIBBLE
24 } state;
25
26 always @(posedge clock) begin
27 if (reset) begin
28 result_ready = 0;
29 echo_valid = 0;
30 echo_data = 0;
31 byte_count = 0;
32 word_count = 0;
33 state = state.first;
34 end else begin
35 if (echo_ready) echo_valid = 0;
36 if (result_ready && result_valid) begin
37 hold = result_data;
38 if (hold.tag == TAG) begin
39 byte_count = `RAM_WORD_BYTES;
40 word_count = `RAM_LINE_WORDS;
41 state = state.first;
42 end
43 end
44
45 if (word_count != 0 && !echo_valid) begin
46 automatic ram_word_t w = hold.data[word_count-1];
47 automatic ram_byte_t b = w[byte_count-1];
48 echo_valid = 1;
49 case (state)
50 HIGH_NIBBLE: echo_data = b[7:4];
51 LOW_NIBBLE: echo_data = b[3:0];
52 endcase
53 if (echo_data < 10)
54 echo_data = echo_data + "0";
55 else
56 echo_data = echo_data + "A" - 10;
57 state = state.next;
58 if (state == state.first) begin
59 byte_count = byte_count - 1;
60 if (byte_count == 0) begin
61 byte_count = `RAM_WORD_BYTES;
62 word_count = word_count - 1;
63 end
64 end
65 end
66
67 result_ready = word_count == 0;
68 end
69 end
70
71endmodule