1 files changed, 28 insertions, 12 deletions

diff --git a/hdl/top.sv b/hdl/top.sv
index ca45aa9..ffe6656 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -34,28 +34,42 @@ module top
 
     //assign clock_out = internal_clock;
 
-    bit rs232_clock = 0;
-    bit [17:0] rs232_div = 0;
+    bit rs232_tx_clock = 0;
+    bit [17:0] rs232_tx_div = 0;
     always @(posedge internal_clock) begin
         if (internal_reset) begin
-            rs232_clock = 0;
-            rs232_div = 0;
+            rs232_tx_clock = 0;
+            rs232_tx_div = 0;
         end else begin
-            if (++rs232_div == 49987) begin // (30MHz/2)/300
-                ++rs232_clock;
-                rs232_div = 0;
+            if (++rs232_tx_div == 130) begin // (30MHz/2)/115200
+                ++rs232_tx_clock;
+                rs232_tx_div = 0;
             end
         end
     end
 
-    assign clock_out = rs232_clock;
+    assign clock_out = rs232_tx_clock;
+
+    bit rs232_rx_clock = 0;
+    bit [4:0] rs232_rx_div = 0;
+    always @(posedge internal_clock) begin
+        if (internal_reset) begin
+            rs232_rx_clock = 0;
+            rs232_rx_div = 0;
+        end else begin
+            if (++rs232_rx_div == 16) begin // (30MHz/2)/(115200*8)
+                ++rs232_rx_clock;
+                rs232_rx_div = 0;
+            end
+        end
+    end
 
     bit         wire_tx_ready;
     bit         wire_tx_valid;
     uart_byte_t wire_tx_data;
 
     rs232_tx wiretx
-        (   .clock(rs232_clock)
+        (   .clock(rs232_tx_clock)
         ,   .reset(internal_reset)
 
         ,   .out_ready(wire_tx_ready)
@@ -73,7 +87,7 @@ module top
         #(  .WIDTH_BITS($bits(uart_byte_t))
         ) fifotx
         (   .clock_in(internal_clock)
-        ,   .clock_out(rs232_clock)
+        ,   .clock_out(rs232_tx_clock)
 
         ,   .in_ready(rs232_tx_ready)
         ,   .in_valid(rs232_tx_valid)
@@ -88,8 +102,10 @@ module top
     bit         wire_rx_valid;
     uart_byte_t wire_rx_data;
 
-    rs232_rx wirerx
-        (   .clock(rs232_clock)
+    rs232_rx
+        #(  .OVERSAMPLE(7)
+        ) wirerx
+        (   .clock(rs232_rx_clock)
         ,   .reset(internal_reset)
 
         ,   .in_ready(wire_rx_ready)