1 files changed, 57 insertions, 61 deletions

diff --git a/hdl/top.sv b/hdl/top.sv
index ffe6656..6512185 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -7,10 +7,14 @@ module top
     ,   inout   wire    [10:1]  gpioa
     ,   inout   wire    [28:13] gpiob
     ,   inout   wire    [40:31] gpioc
-    ,   output  wire            clock_out
 
     ,   output  wire            rs232_tx
     ,   input   wire            rs232_rx
+    ,   output  wire            rs232_rts
+    ,   input   wire            rs232_cts
+
+    ,   output  wire            debug_tx
+    ,   output  wire            debug_rx
 
     ,   output  bit             ram_resetn
     ,   output  bit             ram_csn
@@ -20,11 +24,14 @@ module top
     ,   inout   bit     [7:0]   ram_data
     );
 
+    assign debug_tx = rs232_tx;
+    assign debug_rx = rs232_rx;
+
     bit internal_clock;
     bit internal_reset;
     pll
-        #(  .MULTIPLY_BY(3)
-        ,   .DIVIDE_BY(5)
+        #(  .MULTIPLY_BY(1)
+        ,   .DIVIDE_BY(1)
         ) fastpll
         (   .native_clk(clock)
         ,   .reset_n(resetn)
@@ -32,51 +39,36 @@ module top
         ,   .reset(internal_reset)
         );
 
-    //assign clock_out = internal_clock;
-
-    bit rs232_tx_clock = 0;
-    bit [17:0] rs232_tx_div = 0;
-    always @(posedge internal_clock) begin
+    bit rs232_tx_clock;
+    bit rs232_tx_reset = 1;
+    always @(posedge rs232_tx_clock) begin
         if (internal_reset) begin
-            rs232_tx_clock = 0;
-            rs232_tx_div = 0;
+            rs232_tx_reset = 1;
         end else begin
-            if (++rs232_tx_div == 130) begin // (30MHz/2)/115200
-                ++rs232_tx_clock;
-                rs232_tx_div = 0;
-            end
+            rs232_tx_reset = 0;
         end
     end
 
-    assign clock_out = rs232_tx_clock;
-
-    bit rs232_rx_clock = 0;
-    bit [4:0] rs232_rx_div = 0;
-    always @(posedge internal_clock) begin
-        if (internal_reset) begin
-            rs232_rx_clock = 0;
-            rs232_rx_div = 0;
-        end else begin
-            if (++rs232_rx_div == 16) begin // (30MHz/2)/(115200*8)
-                ++rs232_rx_clock;
-                rs232_rx_div = 0;
-            end
-        end
-    end
+    bit rs232_rx_clock;
+    assign rs232_rx_clock = internal_clock;
 
     bit         wire_tx_ready;
     bit         wire_tx_valid;
     uart_byte_t wire_tx_data;
 
-    rs232_tx wiretx
+    rs232_tx
+        #(  .PARITY(1)
+        ,   .STOP_BITS(2)
+        ) wiretx
         (   .clock(rs232_tx_clock)
-        ,   .reset(internal_reset)
+        ,   .reset(rs232_tx_reset)
 
         ,   .out_ready(wire_tx_ready)
         ,   .out_valid(wire_tx_valid)
         ,   .out_data(wire_tx_data)
 
         ,   .tx(rs232_tx)
+        ,   .cts(rs232_cts)
         );
 
     bit         rs232_tx_ready;
@@ -88,6 +80,7 @@ module top
         ) fifotx
         (   .clock_in(internal_clock)
         ,   .clock_out(rs232_tx_clock)
+        ,   .reset(internal_reset || rs232_tx_reset)
 
         ,   .in_ready(rs232_tx_ready)
         ,   .in_valid(rs232_tx_valid)
@@ -103,16 +96,20 @@ module top
     uart_byte_t wire_rx_data;
 
     rs232_rx
-        #(  .OVERSAMPLE(7)
+        #(  .PARITY(1)
+        ,   .OVERSAMPLE(433)
         ) wirerx
         (   .clock(rs232_rx_clock)
         ,   .reset(internal_reset)
 
+        ,   .clock_out(rs232_tx_clock)
+
         ,   .in_ready(wire_rx_ready)
         ,   .in_valid(wire_rx_valid)
         ,   .in_data(wire_rx_data)
 
         ,   .rx(rs232_rx)
+        ,   .rts(rs232_rts)
         );
 
     bit         rs232_rx_ready;
@@ -122,8 +119,9 @@ module top
     fifo
         #(  .WIDTH_BITS($bits(uart_byte_t))
         ) fiforx
-        (   .clock_in(rs232_clock)
+        (   .clock_in(rs232_rx_clock)
         ,   .clock_out(internal_clock)
+        ,   .reset(internal_reset)
 
         ,   .in_ready(wire_rx_ready)
         ,   .in_valid(wire_rx_valid)
@@ -182,6 +180,7 @@ module top
     bit [7:0]   ram_data_out;
     assign ram_data = ram_data_oe ? ram_data_out : 8'bZ;
 
+/*
     alt_jtag_atlantic
         #(  .INSTANCE_ID(0)
         ,   .LOG2_RXFIFO_DEPTH(10)
@@ -199,6 +198,15 @@ module top
         ,   .t_dav(ram_rx_ready)
         ,   .t_ena(ram_rx_valid)
         );
+*/
+
+    assign ram_tx_ready = rs232_tx_ready;
+    assign rs232_tx_valid = ram_tx_valid;
+    assign rs232_tx_data = ram_tx_data;
+
+    assign rs232_rx_ready = ram_rx_ready;
+    assign ram_rx_valid = rs232_rx_valid;
+    assign ram_rx_data = rs232_rx_data;
 
     echo_arbiter uart0arb
         (   .clock(internal_clock)
@@ -445,9 +453,7 @@ module top
             bit         rx_valid;
             uart_byte_t rx_data;
 
-            core
-                #(  .JTAG_INSTANCE(1+i)
-                ) cpu
+            core cpu
                 (   .clk(internal_clock)
                 ,   .reset(internal_reset)
 
@@ -507,33 +513,23 @@ module top
                 ,   .led_link(local_led_link[i])
                 );
 
-            if (i == `NUM_PDPS-1) begin
-                assign tx_ready = rs232_tx_ready;
-                assign rs232_tx_valid = tx_valid;
-                assign rs232_tx_data = tx_data;
-
-                assign rs232_rx_ready = rx_ready;
-                assign rx_valid = rs232_rx_valid;
-                assign rx_data = rs232_rx_data;
-            end else begin
-                alt_jtag_atlantic
-                    #(  .INSTANCE_ID(1+i)
-                    ,   .LOG2_RXFIFO_DEPTH(10)
-                    ,   .LOG2_TXFIFO_DEPTH(10)
-                    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
-                    ) uart
-                    (   .clk(internal_clock)
-                    ,   .rst_n(!internal_reset)
+            alt_jtag_atlantic
+                #(  .INSTANCE_ID(i)
+                ,   .LOG2_RXFIFO_DEPTH(10)
+                ,   .LOG2_TXFIFO_DEPTH(10)
+                ,   .SLD_AUTO_INSTANCE_INDEX("NO")
+                ) uart
+                (   .clk(internal_clock)
+                ,   .rst_n(!internal_reset)
 
-                    ,   .r_dat(tx_data)
-                    ,   .r_val(tx_valid)
-                    ,   .r_ena(tx_ready)
+                ,   .r_dat(tx_data)
+                ,   .r_val(tx_valid)
+                ,   .r_ena(tx_ready)
 
-                    ,   .t_dat(rx_data)
-                    ,   .t_dav(rx_ready)
-                    ,   .t_ena(rx_valid)
-                    );
-            end
+                ,   .t_dat(rx_data)
+                ,   .t_dav(rx_ready)
+                ,   .t_ena(rx_valid)
+                );
 
         end