4 files changed, 161 insertions, 31 deletions

diff --git a/hdl/core.sv b/hdl/core.sv
index 7fdd20a..6827b8e 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -8,6 +8,14 @@ module core
     (   input   bit clk
     ,   input   bit reset
 
+    ,   input   bit         uart_tx_ready
+    ,   output  bit         uart_tx_valid
+    ,   output  uart_byte_t uart_tx_data
+
+    ,   output  bit         uart_rx_ready
+    ,   input   bit         uart_rx_valid
+    ,   input   uart_byte_t uart_rx_data
+
     ,   input   bit             mem_command_ready
     ,   output  bit             mem_command_valid
     ,   output  pdp_command_t   mem_command
@@ -115,23 +123,12 @@ bit tx_ready;
 bit tx_valid;
 bit [7:0] tx_data;
 
-alt_jtag_atlantic
-    #(  .INSTANCE_ID(JTAG_INSTANCE)
-    ,   .LOG2_RXFIFO_DEPTH(10)
-    ,   .LOG2_TXFIFO_DEPTH(10)
-    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
-    ) uart
-    (   .clk(clk)
-    ,   .rst_n(!reset)
-
-    ,   .r_dat(tx_data)
-    ,   .r_val(tx_valid)
-    ,   .r_ena(tx_ready)
-
-    ,   .t_dat(rx_data)
-    ,   .t_dav(rx_ready)
-    ,   .t_ena(rx_valid)
-    );
+assign tx_ready = uart_tx_ready;
+assign uart_tx_valid = tx_valid;
+assign uart_tx_data = tx_data;
+assign uart_rx_ready = rx_ready;
+assign rx_valid = uart_rx_valid;
+assign rx_data = uart_rx_data;
 
 bit [`PDP_ADDRESS_BITS-3-1:7] page;
 
diff --git a/hdl/defs.svh b/hdl/defs.svh
index 44336eb..3206764 100644
--- a/hdl/defs.svh
+++ b/hdl/defs.svh
@@ -5,7 +5,7 @@
 
 `define PDP_ADDRESS_BITS    15
 
-`define NUM_PDPS            12
+`define NUM_PDPS            2
 
 `define UART_BYTE_BITS      8
 
diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 2f631f8..03378ef 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -20,7 +20,7 @@ module rs232_tx
         ,   STOP
         } state;
 
-    bit [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+    bit [$clog2(`UART_BYTE_BITS):0] data_bits;
 
     always @(posedge clock) begin
         if (reset) begin
@@ -34,7 +34,7 @@ module rs232_tx
                 hold_valid = 1;
                 hold = out_data;
                 state = state.first;
-                data_bits = `UART_BYTE_BITS;
+                data_bits = 0;
             end
 
             if (hold_valid) begin
@@ -46,10 +46,11 @@ module rs232_tx
                     end
 
                     DATA: begin
-                        --data_bits;
-                        tx = !out_data[data_bits];
-                        if (data_bits == 0)
+                        tx = hold[data_bits];
+                        if (data_bits == `UART_BYTE_BITS-1)
                             state = state.next;
+                        else
+                            ++data_bits;
                     end
 
                     STOP: begin
@@ -86,8 +87,8 @@ module rs232_rx
         ,   STOP
         } state;
 
-    uart_byte_t                                 buffer;
-    bit         [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+    uart_byte_t                             buffer;
+    bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
 
     always @(posedge clock) begin
         if (reset) begin
@@ -105,21 +106,22 @@ module rs232_rx
                     if (rx == 0) begin
                         state = state.next;
                         buffer = 0;
-                        data_bits = `UART_BYTE_BITS;
+                        data_bits = 0;
                     end
                 end
 
                 DATA: begin
-                    --data_bits;
-                    buffer[data_bits] = !rx;
-                    if (data_bits == 0)
+                    buffer[data_bits] = rx;
+                    if (data_bits == `UART_BYTE_BITS-1)
                         state = state.next;
+                    else
+                        ++data_bits;
                 end
 
                 STOP: begin
                     if (!in_valid && rx == 1) begin
                         in_valid = 1;
-                        in_data = data_bits;
+                        in_data = buffer;
                     end
                     state = state.next;
                 end
diff --git a/hdl/top.sv b/hdl/top.sv
index 20294ff..ca45aa9 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -9,6 +9,9 @@ module top
     ,   inout   wire    [40:31] gpioc
     ,   output  wire            clock_out
 
+    ,   output  wire            rs232_tx
+    ,   input   wire            rs232_rx
+
     ,   output  bit             ram_resetn
     ,   output  bit             ram_csn
     ,   output  bit             ram_clkp
@@ -29,7 +32,91 @@ module top
         ,   .reset(internal_reset)
         );
 
-    assign clock_out = internal_clock;
+    //assign clock_out = internal_clock;
+
+    bit rs232_clock = 0;
+    bit [17:0] rs232_div = 0;
+    always @(posedge internal_clock) begin
+        if (internal_reset) begin
+            rs232_clock = 0;
+            rs232_div = 0;
+        end else begin
+            if (++rs232_div == 49987) begin // (30MHz/2)/300
+                ++rs232_clock;
+                rs232_div = 0;
+            end
+        end
+    end
+
+    assign clock_out = rs232_clock;
+
+    bit         wire_tx_ready;
+    bit         wire_tx_valid;
+    uart_byte_t wire_tx_data;
+
+    rs232_tx wiretx
+        (   .clock(rs232_clock)
+        ,   .reset(internal_reset)
+
+        ,   .out_ready(wire_tx_ready)
+        ,   .out_valid(wire_tx_valid)
+        ,   .out_data(wire_tx_data)
+
+        ,   .tx(rs232_tx)
+        );
+
+    bit         rs232_tx_ready;
+    bit         rs232_tx_valid;
+    uart_byte_t rs232_tx_data;
+
+    fifo
+        #(  .WIDTH_BITS($bits(uart_byte_t))
+        ) fifotx
+        (   .clock_in(internal_clock)
+        ,   .clock_out(rs232_clock)
+
+        ,   .in_ready(rs232_tx_ready)
+        ,   .in_valid(rs232_tx_valid)
+        ,   .in_data(rs232_tx_data)
+
+        ,   .out_ready(wire_tx_ready)
+        ,   .out_valid(wire_tx_valid)
+        ,   .out_data(wire_tx_data)
+        );
+
+    bit         wire_rx_ready;
+    bit         wire_rx_valid;
+    uart_byte_t wire_rx_data;
+
+    rs232_rx wirerx
+        (   .clock(rs232_clock)
+        ,   .reset(internal_reset)
+
+        ,   .in_ready(wire_rx_ready)
+        ,   .in_valid(wire_rx_valid)
+        ,   .in_data(wire_rx_data)
+
+        ,   .rx(rs232_rx)
+        );
+
+    bit         rs232_rx_ready;
+    bit         rs232_rx_valid;
+    uart_byte_t rs232_rx_data;
+
+    fifo
+        #(  .WIDTH_BITS($bits(uart_byte_t))
+        ) fiforx
+        (   .clock_in(rs232_clock)
+        ,   .clock_out(internal_clock)
+
+        ,   .in_ready(wire_rx_ready)
+        ,   .in_valid(wire_rx_valid)
+        ,   .in_data(wire_rx_data)
+
+        ,   .out_ready(rs232_rx_ready)
+        ,   .out_valid(rs232_rx_valid)
+        ,   .out_data(rs232_rx_data)
+        );
 
     bit         ram_rx_ready;
     bit         ram_rx_valid;
@@ -334,12 +421,28 @@ module top
         genvar i;
         for (i = 0; i < `NUM_PDPS; ++i) begin : core
 
+            bit         tx_ready;
+            bit         tx_valid;
+            uart_byte_t tx_data;
+
+            bit         rx_ready;
+            bit         rx_valid;
+            uart_byte_t rx_data;
+
             core
                 #(  .JTAG_INSTANCE(1+i)
                 ) cpu
                 (   .clk(internal_clock)
                 ,   .reset(internal_reset)
 
+                ,   .uart_tx_ready(tx_ready)
+                ,   .uart_tx_valid(tx_valid)
+                ,   .uart_tx_data(tx_data)
+
+                ,   .uart_rx_ready(rx_ready)
+                ,   .uart_rx_valid(rx_valid)
+                ,   .uart_rx_data(rx_data)
+
                 ,   .mem_command_ready(pdp_command_ready[i])
                 ,   .mem_command_valid(pdp_command_valid[i])
                 ,   .mem_command(pdp_command_data[i])
@@ -388,6 +491,34 @@ module top
                 ,   .led_link(local_led_link[i])
                 );
 
+            if (i == `NUM_PDPS-1) begin
+                assign tx_ready = rs232_tx_ready;
+                assign rs232_tx_valid = tx_valid;
+                assign rs232_tx_data = tx_data;
+
+                assign rs232_rx_ready = rx_ready;
+                assign rx_valid = rs232_rx_valid;
+                assign rx_data = rs232_rx_data;
+            end else begin
+                alt_jtag_atlantic
+                    #(  .INSTANCE_ID(1+i)
+                    ,   .LOG2_RXFIFO_DEPTH(10)
+                    ,   .LOG2_TXFIFO_DEPTH(10)
+                    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
+                    ) uart
+                    (   .clk(internal_clock)
+                    ,   .rst_n(!internal_reset)
+
+                    ,   .r_dat(tx_data)
+                    ,   .r_val(tx_valid)
+                    ,   .r_ena(tx_ready)
+
+                    ,   .t_dat(rx_data)
+                    ,   .t_dav(rx_ready)
+                    ,   .t_ena(rx_valid)
+                    );
+            end
+
         end
 
     endgenerate