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-rw-r--r--hdl/command_parser.sv2
-rw-r--r--hdl/core.sv7
-rw-r--r--hdl/defs.svh12
-rw-r--r--hdl/mem_arbiter.sv8
-rw-r--r--hdl/mem_broadcast.sv8
-rw-r--r--hdl/mem_cache.sv8
-rw-r--r--hdl/ram_controller.sv6
-rw-r--r--hdl/result_printer.sv4
-rw-r--r--hdl/top.sv16
9 files changed, 37 insertions, 34 deletions
diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv
index a4a5190..5be5957 100644
--- a/hdl/command_parser.sv
+++ b/hdl/command_parser.sv
@@ -15,7 +15,7 @@ module command_parser
15 15
16 , input bit command_ready 16 , input bit command_ready
17 , output bit command_valid 17 , output bit command_valid
18 , output ram_command_t command_data 18 , output arb_to_ram_t command_data
19 19
20 , input bit loop_ready 20 , input bit loop_ready
21 , output bit loop_valid 21 , output bit loop_valid
diff --git a/hdl/core.sv b/hdl/core.sv
index 587ffeb..5f264d9 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -16,11 +16,11 @@ module core
16 16
17 , input bit mem_command_ready 17 , input bit mem_command_ready
18 , output bit mem_command_valid 18 , output bit mem_command_valid
19 , output pdp_command_t mem_command 19 , output core_to_mem_t mem_command
20 20
21 , output bit mem_read_ready 21 , output bit mem_read_ready
22 , input bit mem_read_valid 22 , input bit mem_read_valid
23 , input pdp_read_response_t mem_read 23 , input mem_to_core_t mem_read
24 24
25 , input bit [2:0] switch_df 25 , input bit [2:0] switch_df
26 , input bit [2:0] switch_if 26 , input bit [2:0] switch_if
@@ -109,9 +109,10 @@ assign led_current_address = mem_command_valid;
109assign led_memaddr = mem_command.address[`PDP_ADDRESS_BITS-3-1:0]; 109assign led_memaddr = mem_command.address[`PDP_ADDRESS_BITS-3-1:0];
110 110
111assign mem_command.mask = ~0; 111assign mem_command.mask = ~0;
112assign mem_command.snoop_response = 0;
112 113
113bit mem_hold_valid; 114bit mem_hold_valid;
114pdp_read_response_t mem_hold; 115mem_to_core_t mem_hold;
115 116
116bit rx_ready; 117bit rx_ready;
117bit rx_valid; 118bit rx_valid;
diff --git a/hdl/defs.svh b/hdl/defs.svh
index f8b1032..73fddaf 100644
--- a/hdl/defs.svh
+++ b/hdl/defs.svh
@@ -5,7 +5,7 @@
5 5
6`define PDP_ADDRESS_BITS 15 6`define PDP_ADDRESS_BITS 15
7 7
8`define NUM_PDPS 1 8`define NUM_PDPS 4
9 9
10`define UART_BYTE_BITS 8 10`define UART_BYTE_BITS 8
11 11
@@ -37,22 +37,24 @@ typedef struct packed {
37 ram_line_t data; 37 ram_line_t data;
38 ram_line_mask_t mask; 38 ram_line_mask_t mask;
39 tag_t tag; 39 tag_t tag;
40} ram_command_t; 40} arb_to_ram_t;
41 41
42typedef struct packed { 42typedef struct packed {
43 ram_line_address_t address; 43 ram_line_address_t address;
44 ram_line_t data; 44 ram_line_t data;
45 tag_t tag; 45 tag_t tag;
46} ram_read_response_t; 46} ram_to_arb_t;
47 47
48typedef struct packed { 48typedef struct packed {
49 pdp_line_address_t address; 49 pdp_line_address_t address;
50 bit write; 50 bit write;
51 bit snoop_response;
51 ram_line_t data; 52 ram_line_t data;
52 ram_line_mask_t mask; 53 ram_line_mask_t mask;
53} pdp_command_t; 54} core_to_mem_t;
54 55
55typedef struct packed { 56typedef struct packed {
56 pdp_line_address_t address; 57 pdp_line_address_t address;
58 bit snoop;
57 ram_line_t data; 59 ram_line_t data;
58} pdp_read_response_t; 60} mem_to_core_t;
diff --git a/hdl/mem_arbiter.sv b/hdl/mem_arbiter.sv
index 854867f..a9d7212 100644
--- a/hdl/mem_arbiter.sv
+++ b/hdl/mem_arbiter.sv
@@ -6,19 +6,19 @@ module mem_arbiter
6 6
7 , output bit command_ready 7 , output bit command_ready
8 , input bit command_valid 8 , input bit command_valid
9 , input ram_command_t command_data 9 , input arb_to_ram_t command_data
10 10
11 , output bit [`NUM_PDPS-1:0] pdp_ready 11 , output bit [`NUM_PDPS-1:0] pdp_ready
12 , input bit [`NUM_PDPS-1:0] pdp_valid 12 , input bit [`NUM_PDPS-1:0] pdp_valid
13 , input pdp_command_t [`NUM_PDPS-1:0] pdp_data 13 , input core_to_mem_t [`NUM_PDPS-1:0] pdp_data
14 14
15 , input bit ram_ready 15 , input bit ram_ready
16 , output bit ram_valid 16 , output bit ram_valid
17 , output ram_command_t ram_data 17 , output arb_to_ram_t ram_data
18 ); 18 );
19 19
20 bit [`NUM_PDPS:0] hold_valid; 20 bit [`NUM_PDPS:0] hold_valid;
21 ram_command_t [`NUM_PDPS:0] hold_data; 21 arb_to_ram_t [`NUM_PDPS:0] hold_data;
22 22
23 bit [$clog2(`NUM_PDPS+1):0] selector; 23 bit [$clog2(`NUM_PDPS+1):0] selector;
24 24
diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv
index 720699b..599be28 100644
--- a/hdl/mem_broadcast.sv
+++ b/hdl/mem_broadcast.sv
@@ -6,19 +6,19 @@ module mem_broadcast
6 6
7 , output bit ram_ready 7 , output bit ram_ready
8 , input bit ram_valid 8 , input bit ram_valid
9 , input ram_read_response_t ram_data 9 , input ram_to_arb_t ram_data
10 10
11 , input bit print_ready 11 , input bit print_ready
12 , output bit print_valid 12 , output bit print_valid
13 , output ram_read_response_t print_data 13 , output ram_to_arb_t print_data
14 14
15 , input bit [`NUM_PDPS-1:0] pdp_ready 15 , input bit [`NUM_PDPS-1:0] pdp_ready
16 , output bit [`NUM_PDPS-1:0] pdp_valid 16 , output bit [`NUM_PDPS-1:0] pdp_valid
17 , output pdp_read_response_t [`NUM_PDPS-1:0] pdp_data 17 , output mem_to_core_t [`NUM_PDPS-1:0] pdp_data
18 ); 18 );
19 19
20 bit hold_valid; 20 bit hold_valid;
21 ram_read_response_t hold_data; 21 ram_to_arb_t hold_data;
22 22
23 always @(posedge clock) begin 23 always @(posedge clock) begin
24 if (reset) begin 24 if (reset) begin
diff --git a/hdl/mem_cache.sv b/hdl/mem_cache.sv
index 2257a4f..181d8d7 100644
--- a/hdl/mem_cache.sv
+++ b/hdl/mem_cache.sv
@@ -10,19 +10,19 @@ module mem_cache
10 10
11 , output bit core_command_ready 11 , output bit core_command_ready
12 , input bit core_command_valid 12 , input bit core_command_valid
13 , input pdp_command_t core_command_data 13 , input core_to_mem_t core_command_data
14 14
15 , input bit ram_command_ready 15 , input bit ram_command_ready
16 , output bit ram_command_valid 16 , output bit ram_command_valid
17 , output pdp_command_t ram_command_data 17 , output core_to_mem_t ram_command_data
18 18
19 , output bit ram_response_ready 19 , output bit ram_response_ready
20 , input bit ram_response_valid 20 , input bit ram_response_valid
21 , input pdp_read_response_t ram_response_data 21 , input mem_to_core_t ram_response_data
22 22
23 , input bit core_response_ready 23 , input bit core_response_ready
24 , output bit core_response_valid 24 , output bit core_response_valid
25 , output pdp_read_response_t core_response_data 25 , output mem_to_core_t core_response_data
26 ); 26 );
27 27
28 localparam ADDRESS_TAG_LO = $clog2(`RAM_LINE_WORDS)+SET_BITS; 28 localparam ADDRESS_TAG_LO = $clog2(`RAM_LINE_WORDS)+SET_BITS;
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 14a1609..c67edc3 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -9,11 +9,11 @@ module ram_controller
9 9
10 , output bit command_ready 10 , output bit command_ready
11 , input bit command_valid 11 , input bit command_valid
12 , input ram_command_t command_data 12 , input arb_to_ram_t command_data
13 13
14 , input bit result_ready 14 , input bit result_ready
15 , output bit result_valid 15 , output bit result_valid
16 , output ram_read_response_t result_data 16 , output ram_to_arb_t result_data
17 17
18 , output bit ram_resetn 18 , output bit ram_resetn
19 , output bit ram_csn 19 , output bit ram_csn
@@ -30,7 +30,7 @@ module ram_controller
30 assign ram_clkn = !ram_clkp; 30 assign ram_clkn = !ram_clkp;
31 31
32 bit valid; 32 bit valid;
33 ram_command_t command; 33 arb_to_ram_t command;
34 ram_word_address_t base_address; 34 ram_word_address_t base_address;
35 35
36 bit slow; 36 bit slow;
diff --git a/hdl/result_printer.sv b/hdl/result_printer.sv
index 322fac0..f9910f9 100644
--- a/hdl/result_printer.sv
+++ b/hdl/result_printer.sv
@@ -6,7 +6,7 @@ module result_printer
6 6
7 , output bit result_ready 7 , output bit result_ready
8 , input bit result_valid 8 , input bit result_valid
9 , input ram_read_response_t result_data 9 , input ram_to_arb_t result_data
10 10
11 , input bit echo_ready 11 , input bit echo_ready
12 , output bit echo_valid 12 , output bit echo_valid
@@ -18,7 +18,7 @@ module result_printer
18 ); 18 );
19 19
20 bit hold_valid; 20 bit hold_valid;
21 ram_read_response_t hold; 21 ram_to_arb_t hold;
22 bit loop; 22 bit loop;
23 ram_byte_count_t byte_count; 23 ram_byte_count_t byte_count;
24 ram_word_count_t word_count; 24 ram_word_count_t word_count;
diff --git a/hdl/top.sv b/hdl/top.sv
index 5f98ff9..96b7510 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -155,19 +155,19 @@ module top
155 155
156 bit command_ready; 156 bit command_ready;
157 bit command_valid; 157 bit command_valid;
158 ram_command_t command_data; 158 arb_to_ram_t command_data;
159 159
160 bit ram_command_ready; 160 bit ram_command_ready;
161 bit ram_command_valid; 161 bit ram_command_valid;
162 ram_command_t ram_command_data; 162 arb_to_ram_t ram_command_data;
163 163
164 bit ram_response_ready; 164 bit ram_response_ready;
165 bit ram_response_valid; 165 bit ram_response_valid;
166 ram_read_response_t ram_response_data; 166 ram_to_arb_t ram_response_data;
167 167
168 bit print_ready; 168 bit print_ready;
169 bit print_valid; 169 bit print_valid;
170 ram_read_response_t print_data; 170 ram_to_arb_t print_data;
171 171
172 bit loop_ready; 172 bit loop_ready;
173 bit loop_valid; 173 bit loop_valid;
@@ -175,11 +175,11 @@ module top
175 175
176 bit [`NUM_PDPS-1:0] pdp_command_ready; 176 bit [`NUM_PDPS-1:0] pdp_command_ready;
177 bit [`NUM_PDPS-1:0] pdp_command_valid; 177 bit [`NUM_PDPS-1:0] pdp_command_valid;
178 pdp_command_t [`NUM_PDPS-1:0] pdp_command_data; 178 core_to_mem_t [`NUM_PDPS-1:0] pdp_command_data;
179 179
180 bit [`NUM_PDPS-1:0] pdp_response_ready; 180 bit [`NUM_PDPS-1:0] pdp_response_ready;
181 bit [`NUM_PDPS-1:0] pdp_response_valid; 181 bit [`NUM_PDPS-1:0] pdp_response_valid;
182 pdp_read_response_t [`NUM_PDPS-1:0] pdp_response_data; 182 mem_to_core_t [`NUM_PDPS-1:0] pdp_response_data;
183 183
184 bit ram_rwds_oe; 184 bit ram_rwds_oe;
185 bit ram_rwds_out; 185 bit ram_rwds_out;
@@ -476,11 +476,11 @@ module top
476 476
477 bit cache_command_ready; 477 bit cache_command_ready;
478 bit cache_command_valid; 478 bit cache_command_valid;
479 pdp_command_t cache_command_data; 479 core_to_mem_t cache_command_data;
480 480
481 bit cache_response_ready; 481 bit cache_response_ready;
482 bit cache_response_valid; 482 bit cache_response_valid;
483 pdp_read_response_t cache_response_data; 483 mem_to_core_t cache_response_data;
484 484
485`ifdef NO_L1_CACHE 485`ifdef NO_L1_CACHE
486 assign cache_command_ready = pdp_command_ready[i]; 486 assign cache_command_ready = pdp_command_ready[i];