4 files changed, 156 insertions, 9 deletions

diff --git a/hdl/defs.svh b/hdl/defs.svh
index f4590c8..f8b1032 100644
--- a/hdl/defs.svh
+++ b/hdl/defs.svh
@@ -5,7 +5,7 @@
 
 `define PDP_ADDRESS_BITS    15
 
-`define NUM_PDPS            16
+`define NUM_PDPS            1
 
 `define UART_BYTE_BITS      8
 
diff --git a/hdl/fifo.sv b/hdl/fifo.sv
index 19877c4..9399006 100644
--- a/hdl/fifo.sv
+++ b/hdl/fifo.sv
@@ -1,6 +1,6 @@
 module fifo
     #(  WIDTH_BITS  = 1
-    ,   DEPTH_BITS  = 10
+    ,   DEPTH_BITS  = 8
     )
     (   input   bit     clock_in
     ,   input   bit     clock_out
@@ -21,7 +21,7 @@ module fifo
     typedef bit [DEPTH_BITS-1:0]    addr_t;
     typedef bit [DEPTH_BITS:0]      grey_t;
 
-    data_t  data    [DEPTH-1:0];
+    (* ramstyle = "no_rw_check, M9K" *) data_t  data    [DEPTH-1:0];
 
     addr_t  oldest, youngest;
     bit     oldest_wrap, youngest_wrap;
diff --git a/hdl/mem_cache.sv b/hdl/mem_cache.sv
new file mode 100644
index 0000000..5f3db73
--- /dev/null
+++ b/hdl/mem_cache.sv
@@ -0,0 +1,108 @@
+`include "defs.svh"
+
+module mem_cache
+    #(  SET_BITS    = 8
+    )
+    (   input   bit clock
+    ,   input   bit reset
+
+    ,   output  bit             core_command_ready
+    ,   input   bit             core_command_valid
+    ,   input   pdp_command_t   core_command_data
+
+    ,   input   bit             ram_command_ready
+    ,   output  bit             ram_command_valid
+    ,   output  pdp_command_t   ram_command_data
+
+    ,   output  bit                 ram_response_ready
+    ,   input   bit                 ram_response_valid
+    ,   input   pdp_read_response_t ram_response_data
+
+    ,   input   bit                 core_response_ready
+    ,   output  bit                 core_response_valid
+    ,   output  pdp_read_response_t core_response_data
+    );
+
+    localparam ADDRESS_TAG_LO   = $clog2(`RAM_LINE_WORDS)+SET_BITS;
+
+    typedef bit [`PDP_ADDRESS_BITS-1:ADDRESS_TAG_LO]        address_tag_t;
+    typedef bit [ADDRESS_TAG_LO-1:$clog2(`RAM_LINE_WORDS)]  set_t;
+
+    typedef struct packed {
+        bit             valid;
+        address_tag_t   address;
+    } tag_t;
+
+    typedef struct packed {
+        tag_t       tag;
+        ram_line_t  data;
+    } cache_entry_t;
+
+    (* ramstyle = "no_rw_check, M9K" *) cache_entry_t   cache   [(1<<SET_BITS)-1:0];
+
+    bit outstanding_fill;
+
+    bit [SET_BITS:0]    reset_entry;
+
+    always @(posedge clock) begin
+        if (reset) begin
+            core_command_ready = 0;
+            ram_command_valid = 0;
+            ram_response_ready = 0;
+            core_response_valid = 0;
+            outstanding_fill = 0;
+            reset_entry = 0;
+        end else if (reset_entry < (1<<SET_BITS)) begin
+            cache[reset_entry] = 0;
+            ++reset_entry;
+        end else begin
+            if (ram_command_ready && ram_command_valid)
+                ram_command_valid = 0;
+            if (core_response_ready && core_response_valid)
+                core_response_valid = 0;
+
+            if (ram_response_ready && ram_response_valid) begin
+                automatic address_tag_t tag;
+                automatic set_t set;
+                automatic cache_entry_t entry;
+                {tag, set} = ram_response_data.address;
+                entry.tag.valid = 1;
+                entry.tag.address = tag;
+                entry.data = ram_response_data.data;
+                cache[set] = entry;
+                core_response_valid = 1;
+                core_response_data = ram_response_data;
+                outstanding_fill = 0;
+            end else if (core_command_ready && core_command_valid) begin
+                automatic address_tag_t tag;
+                automatic set_t set;
+                {tag, set} = core_command_data.address;
+                if (core_command_data.write) begin
+                    automatic cache_entry_t entry;
+                    entry.tag.valid = 1;
+                    entry.tag.address = tag;
+                    // FIXME masked stores
+                    entry.data = core_command_data.data;
+                    cache[set] = entry;
+                    ram_command_valid = 1;
+                    ram_command_data = core_command_data;
+                end else begin
+                    automatic cache_entry_t entry = cache[set];
+                    if (entry.tag.valid && entry.tag.address == tag) begin
+                        core_response_valid = 1;
+                        core_response_data.address = {tag, set};
+                        core_response_data.data = entry.data;
+                    end else begin
+                        ram_command_valid = 1;
+                        ram_command_data = core_command_data;
+                        outstanding_fill = 1;
+                    end
+                end
+            end
+
+            core_command_ready = !ram_command_valid && !core_response_valid && !outstanding_fill;
+            ram_response_ready = !core_response_valid;
+        end
+    end
+
+endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
index 03a2331..26006be 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -470,6 +470,45 @@ module top
             bit         rx_valid;
             uart_byte_t rx_data;
 
+            bit             cache_command_ready;
+            bit             cache_command_valid;
+            pdp_command_t   cache_command_data;
+
+            bit                 cache_response_ready;
+            bit                 cache_response_valid;
+            pdp_read_response_t cache_response_data;
+
+`ifdef NO_L1_CACHE
+            assign cache_command_ready = pdp_command_ready[i];
+            assign pdp_command_valid[i] = cache_command_valid;
+            assign pdp_command_data[i] = cache_command_data;
+
+            assign pdp_response_ready[i] = cache_response_ready;
+            assign cache_response_valid = pdp_response_valid[i];
+            assign cache_response_data = pdp_response_data[i];
+`else
+            mem_cache cache
+                (   .clock(internal_clock)
+                ,   .reset(internal_reset)
+
+                ,   .core_command_ready(cache_command_ready)
+                ,   .core_command_valid(cache_command_valid)
+                ,   .core_command_data(cache_command_data)
+
+                ,   .ram_command_ready(pdp_command_ready[i])
+                ,   .ram_command_valid(pdp_command_valid[i])
+                ,   .ram_command_data(pdp_command_data[i])
+
+                ,   .ram_response_ready(pdp_response_ready[i])
+                ,   .ram_response_valid(pdp_response_valid[i])
+                ,   .ram_response_data(pdp_response_data[i])
+
+                ,   .core_response_ready(cache_response_ready)
+                ,   .core_response_valid(cache_response_valid)
+                ,   .core_response_data(cache_response_data)
+                );
+`endif
+
             core cpu
                 (   .clk(internal_clock)
                 ,   .reset(internal_reset)
@@ -482,13 +521,13 @@ module top
                 ,   .uart_rx_valid(rx_valid)
                 ,   .uart_rx_data(rx_data)
 
-                ,   .mem_command_ready(pdp_command_ready[i])
-                ,   .mem_command_valid(pdp_command_valid[i])
-                ,   .mem_command(pdp_command_data[i])
+                ,   .mem_command_ready(cache_command_ready)
+                ,   .mem_command_valid(cache_command_valid)
+                ,   .mem_command(cache_command_data)
 
-                ,   .mem_read_ready(pdp_response_ready[i])
-                ,   .mem_read_valid(pdp_response_valid[i])
-                ,   .mem_read(pdp_response_data[i])
+                ,   .mem_read_ready(cache_response_ready)
+                ,   .mem_read_valid(cache_response_valid)
+                ,   .mem_read(cache_response_data)
 
                 ,   .switch_df(0)
                 ,   .switch_if(0)