| Commit message (Expand) | Author | Files | Lines | |
|---|---|---|---|---|
| 2022-03-27 | Update PLAN. | Julian Blake Kongslie | 1 | -13/+10 |
| 2022-03-27 | 12 PDP-8s! :-) | Julian Blake Kongslie | 1 | -1/+1 |
| 2022-03-27 | A more-fair memory arbiter that actually works. | Julian Blake Kongslie | 1 | -31/+34 |
| 2022-03-27 | Add RX/TX/RTS/CTS pin assignments for future RS232 work. | Julian Blake Kongslie | 1 | -0/+5 |
| 2022-03-27 | Use the DF and IF switches as a selector for which PDP-8 owns the panel. | Julian Blake Kongslie | 1 | -89/+92 |
| 2022-03-27 | Add a clock output pin for debugging the PLL. | Julian Blake Kongslie | 2 | -0/+5 |
| 2022-03-27 | Attempt to make somewhat less error-prone downloads. | Julian Blake Kongslie | 2 | -6/+5 |
| 2022-03-27 | Reduce internal clock speed to 30MHz. | Julian Blake Kongslie | 2 | -3/+3 |
| 2022-03-27 | Attempt to download for 16 PDP-8s. | Julian Blake Kongslie | 1 | -8/+16 |
| 2022-03-27 | Don't use SystemVerilog parametric types because Altera doesn't support them. | Julian Blake Kongslie | 1 | -9/+9 |
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index : multipdp8 | |
| Unnamed repository; edit this file 'description' to name the repository. | Julian Blake Kongslie |
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