summaryrefslogtreecommitdiff
path: root/altera/clocks.sdc (unfollow)
Commit message (Expand)AuthorFilesLines
2022-04-17Fix whitespace/maxlinesize handling in p8bin2uart.Julian Blake Kongslie1-8/+7
2022-04-17Working (but very slow) RS232 UARTJulian Blake Kongslie5-35/+165
2022-03-28Integrate wrap bits into grey code for FIFO.Julian Blake Kongslie1-5/+8
2022-03-27Update PLAN.Julian Blake Kongslie1-13/+10
2022-03-2712 PDP-8s! :-)Julian Blake Kongslie1-1/+1
2022-03-27A more-fair memory arbiter that actually works.Julian Blake Kongslie1-31/+34
2022-03-27Add RX/TX/RTS/CTS pin assignments for future RS232 work.Julian Blake Kongslie1-0/+5
2022-03-27Use the DF and IF switches as a selector for which PDP-8 owns the panel.Julian Blake Kongslie1-89/+92
2022-03-27Add a clock output pin for debugging the PLL.Julian Blake Kongslie2-0/+5
2022-03-27Attempt to make somewhat less error-prone downloads.Julian Blake Kongslie2-6/+5
2022-03-27Reduce internal clock speed to 30MHz.Julian Blake Kongslie2-3/+3
2022-03-27Attempt to download for 16 PDP-8s.Julian Blake Kongslie1-8/+16
2022-03-27Don't use SystemVerilog parametric types because Altera doesn't support them.Julian Blake Kongslie1-9/+9