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2022-05-22Update PLAN.Julian Blake Kongslie1-6/+5
2022-05-22Two-cycle memory arbiter, enabling 16 PDP-8s @ 50MHz.Julian Blake Kongslie2-14/+12
2022-05-22Only sample RS232 signals once per clock; use a delayed flop internally.Julian Blake Kongslie1-9/+19
This removes metastability issues on inputs and makes everything work.
2022-05-15Update plan.Julian Blake Kongslie1-10/+6
2022-05-15Significantly wider line size for data downloads.Julian Blake Kongslie1-1/+1
8.5sec for 16 cores!
2022-05-15Fix the RS232 receive state machine 😠💢:mad:Julian Blake Kongslie1-1/+1
Our current consensus is that we have a bug which causes the RX state machine to make incomprehensible jumps when the sample counter is more than about 9 bits wide. We haven't completely pinned down the problem; we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter. I hate Verilog and Altera, both exclusively and in combination.
2022-05-15Change to 1Mbaud RS232Julian Blake Kongslie2-2/+2
2022-05-15Only phase shift the RS232 tx clock when we are between bytes.Julian Blake Kongslie2-1/+22
2022-05-15Consistent RS232 wire names (DCE side names is used everywhere)Julian Blake Kongslie3-39/+39
2022-05-15Change makefile to unconditionally load memory for 16 PDP-8sJulian Blake Kongslie1-14/+14
2022-05-08Remove extraneous newline (we still have some other one somewhere)Julian Blake Kongslie1-1/+1
2022-05-08Make the calculation for OVERSAMPLE more explicit.Julian Blake Kongslie1-1/+1
2022-05-08Demand that CTS is asserted for multiple symbol periods before transmit.Julian Blake Kongslie1-1/+8
2022-05-08*Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.Julian Blake Kongslie11-132/+322
2022-04-24Make the script for setting up the TTY actually connect.Julian Blake Kongslie1-0/+6